MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 418

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
9.4.1.11
The DDR SDRAM mode control register, shown in
tasks:
Table 9-16
register to accomplish the above tasks.
Table 9-16
9-24
Offset 0x120
Reset
Bits
2–3
0
1
4
W
•
•
•
•
R
MD_EN — CS_SEL — MD_SEL SET_REF SET_PRE CKE_CNTL
Issue a mode register set command to a particular chip select
Issue an immediate refresh to a particular chip select
Issue an immediate precharge or precharge all command to a particular chip select
Force the CKE signals to a specific value
CS_SEL
MD_EN
0
Name
—
—
describes the fields of this register.
describes the DDR_SDRAM_MD_CNTL fields.
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
Note that MD_EN, SET_REF, and SET_PRE are mutually exclusive; only
one of these fields can be set at a time.
Figure 9-12. DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)
Mode enable. Setting this bit specifies that valid data in MD_VALUE is ready to be written to DRAM as one
of the following commands:
The specific command to be executed is selected by setting MD_SEL. In addition, the chip select must be
chosen by setting CS_SEL. MD_EN is set by software and cleared by hardware once the command has
been issued.
0 Indicates that no mode register set command needs to be issued.
1 Indicates that valid data contained in the register is ready to be issued as a mode register set command.
Reserved
Select chip select. Specifies the chip select that is driven active due to any command forced by software in
DDR_SDRAM_MD_CNTL.
00 Chip select 0 is active
01 Chip select 1 is active
10 Reserved
11 Reserved
Reserved
2
• MODE REGISTER SET
• EXTENDED MODE REGISTER SET
• EXTENDED MODE REGISTER SET 2
• EXTENDED MODE REGISTER SET 3
3
4
Table 9-16. DDR_SDRAM_MD_CNTL Field Descriptions
5
7
8
Table 9-17
9
NOTE
Figure
All zeros
10
Description
shows the user how to set the fields of this
9-12, allows the user to carry out the following
11
12
—
13
15 16
Freescale Semiconductor
MD_VALUE
Access: Read/Write
31