MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 9

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
5.8.2.3
5.8.2.4
5.8.2.5
5.8.3
5.8.3.1
5.8.3.2
5.8.3.3
5.8.3.4
5.8.3.5
5.8.3.5.1
5.8.3.5.2
5.8.3.6
5.8.3.6.1
5.8.3.6.2
5.8.3.7
5.8.3.7.1
5.8.3.7.2
5.8.3.7.3
5.8.3.7.4
5.8.4
5.8.4.1
6.1
6.1.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Overview.......................................................................................................................... 6-1
Arbiter Memory Map/Register Definition ....................................................................... 6-2
Functional Description................................................................................................... 6-10
Functional Description............................................................................................... 5-72
Initialization/Application Information ....................................................................... 5-91
Coherent System Bus Overview .................................................................................. 6-1
Arbiter Configuration Register (ACR) ........................................................................ 6-2
Arbiter Timers Register (ATR) .................................................................................... 6-4
Arbiter Event Register (AER)...................................................................................... 6-5
Arbiter Interrupt Definition Register (AIDR).............................................................. 6-6
Arbiter Mask Register (AMR)..................................................................................... 6-7
Arbiter Event Attributes Register (AEATR)................................................................ 6-7
Arbiter Event Address Register (AEADR).................................................................. 6-9
Arbiter Event Response Register (AERR)................................................................. 6-10
Arbitration Policy ...................................................................................................... 6-10
Power Management Controller Mask Register (PMCMR) ................................... 5-69
Power Management Controller Configuration Register 1 (PMCCR1).................. 5-69
Power Management Controller Configuration Register 2 (PMCCR2).................. 5-71
Dynamic Power Management................................................................................ 5-72
Shutting Down Unused Blocks.............................................................................. 5-73
Software-Controlled Power-Down States.............................................................. 5-73
Software-Controlled Power Supply Switching...................................................... 5-73
Support of PCI Power Management Interface Specification................................. 5-74
Exiting Core and System Low Power States ......................................................... 5-78
MPC8313E-Specific PMC Low Power States ...................................................... 5-79
Core Disable in Low Power Mode ........................................................................ 5-91
Address Bus Arbitration with PRIORITY[0:1] ..................................................... 6-11
Address Bus Arbitration with REPEAT ................................................................ 6-12
Address Bus Arbitration after ARTRY.................................................................. 6-13
Entering Low Power States—Core-Only Mode ................................................ 5-77
Entering Low Power States—Core and System Mode...................................... 5-77
Exiting Low Power States—Core-Only Mode .................................................. 5-78
Exiting Low Power States—Core and System Mode........................................ 5-78
Power State Transitions from an ACPI Perspective .......................................... 5-79
MPC8313E Low Power Sequencing ................................................................. 5-83
PMC External Power Supply Control ............................................................... 5-88
Low-Power Considerations ............................................................................... 5-90
Arbiter and Bus Monitor
Contents
Chapter 6
Title
Number
Page
ix