MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 686

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
Table 14-13
14.4.3.5
The AESU status register (AESUSR), shown in
of six status outputs. Writing to this location will result in an address error being reflected in the AESU
interrupt status register (AESUISR).
Table 14-28
14-44
40–47
48–55
56–57
0–60
0–39
Bits
Bits
61
62
63
Reset
Field
Addr
R/W
Names
Name
OFL
SR
IFL
MI
—
—
—
RI
describes AESURCR fields.
describes AESUSR fields.
AESU Status Register (AESUSR)
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
Reset interrupt. Writing this bit active high causes AESU interrupts signaling DONE and ERROR to be reset.
It further resets the state of the AESU interrupt status register (AESUISR).
0 Do not reset
1 Reset interrupt logic
Module initialization is nearly the same as software reset, except that the interrupt control register remains
unchanged. This module initialization includes execution of an initialization routine, completion of which is
indicated by the RESET_DONE bit in the AESU status register (AESUSR)
0 Do not reset
1 Reset most of AESU
Software reset is functionally equivalent to hardware reset (the RESET# pin), but only for AESU. All registers
and internal state are returned to their defined reset state. Upon negation of SW_RESET, the AESU will enter
a routine to perform proper initialization of the parameter memories. The RESET_DONE bit in the AESU
status register will indicate when this initialization routine is complete
0 Do not reset
1 Full AESU reset
Reserved
The number of dwords currently in the output FIFO
The number of dwords currently in the input FIFO
Reserved
—
39
40
Figure 14-30. AESU Status Register (AESUSR)
Table 14-27. AESURCR Field Descriptions
Table 14-28. AESUSR Field Descriptions
OFL
47
48
IFL
Figure
AESU 0x3_4028
55
Description
Description
14-30, is a read-only register that reflects the state
R
0
56
—
57
HALT
58
59
ICR
60
Freescale Semiconductor
61
IE
ID
62
RD
63