MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1105

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

17.5.2
A hard reset initializes all of the I
initializes the I
17.5.3
After initialization, the following sequence can be used to generate START:
The scenario above assumes that the I
an I
17.5.4
Transmission or reception of a byte automatically sets the data transferring bit (I2CnSR[MCF]), which
indicates that one byte has been transferred. The I
interrupt is generated to the processor if the interrupt function is enabled during the initialization sequence
(I2CnCR[MIEN] is set). In the interrupt handler, software must take the following steps:
If the interrupt function is disabled, software can service the I2CnDR in the main program by monitoring
I2CnSR[MIF]. In this case, I2CnSR[MIF] must be polled rather than I2CnSR[MCF] because MCF
behaves differently when arbitration is lost. Note that interrupt or other bus conditions may be detected
before the I
software delays may be needed to give the I
Freescale Semiconductor
1. All I
2. Update I2CnFDR[FDR] and select the required division ratio to obtain the SCLn frequency from
3. Update I2CnADR to define the slave address for this device.
4. Modify I2CnCR to select master/slave mode, transmit/receive mode, and interrupt-enable or
5. Set the I2CnCR[MEN] to enable the I
1. If the device is connected to a multimaster I
2. Select master mode (set I2CnCR[MSTA]) to transmit serial data and select transmit mode (set
3. Write the slave address being called into I2CnDR. The data written to I2CnDR[0–6] comprises the
2
1. Clear I2CnSR[MIF]
2. Read the I2CnDR in receive mode or write to I2CnDR in transmit mode. Note that this causes
3. When an interrupt occurs at the end of the address cycle, the master remains in transmit mode. If
C interrupt is generated (provided interrupt reporting is enabled with I2CnCR[MIEN] =1).
the CSB (platform) clock.
disable.
(I2CnSR[MBB] = 0) before switching to master mode.
I2CnCR[MTX]) for the address cycle.
slave calling address. I2CnCR[MTX] indicates the direction of transfer (transmit/receive) required
from the slave.
I2CnSR[MCF] to be cleared, as shown in
master receive mode is required, I2CnCR[MTX] must be toggled at this stage (see
2
Initialization Sequence
Generation of START
Post-Transfer Software Response
2
C signals have time to settle. Thus, when polling I2CnSR[MIF] (or any other I2CnSR bits),
C registers must be located in a cache-inhibited page.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C unit:
2
C registers to their default states. The following initialization sequence
2
C interrupt bit (I2CnSR[MIF]) is cleared. If MIF is set at any time,
2
C signals sufficient time to settle.
2
C interface.
Figure
2
C interrupt bit (I2CnSR[MIF]) is also set and an
2
C system, check whether the serial bus is free
17-11.
Figure
I
2
C Interfaces
17-11).
17-21