MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 173

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The device is now in its ready state.
Freescale Semiconductor
5. The device samples the reset configuration input signals to determine the clock division and the
6. The device starts loading the reset configuration words.
7. When the reset configuration word low is loaded, the system PLL begins to lock.
8. The core PLL begins to lock.
9. The device drives HRESET asserted until the e300 PLL is locked and the reset configuration words
10. The user optionally negates HRESET if it was not negated earlier.
11. The internal reset to the core and the rest of the logic is negated. I/O drivers are enabled. The PCI
12. The device stops driving HRESET. The reset to the e300 core is negated and the core is
13. Before the boot sequencer finishes, it can enable the PCI interface to accept external requests, if
14. The PCI interface can now accept external requests, if enabled, and the boot vector fetch by the
reset configuration words source.
Loading time depends on the reset configuration word source.
When the system PLL is locked, csb_clk is supplied to the core PLL.
are loaded.
JTAG logic must always be initialized by asserting TRST. If the JTAG signals are not used, TRST
should be connected directly to PORESET. TRST must not remain asserted after the negation of
PORESET. There is no need to assert the SRESET signal when HRESET is asserted.
interface can assert DEVSEL in response to configuration cycles.
enabled.The boot sequencer, if enabled, is released, causing it to load configuration data from serial
ROMs, as described in
required, by clearing the CFG_LOCK bit in the PCI function configuration register as described in
Table
fetch by clearing ACR[COREDIS] as described in
(ACR).”
core can proceed, if enabled.
13-40. If the e300 core is required to proceed, the boot sequencer should enable boot vector
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 17.4.5, “Boot Sequencer Mode.”
Section 6.2.1, “Arbiter Configuration Register
Reset, Clocking, and Initialization
4-7