MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 614

Manufacturer Part Number

MPC8313ZQADDC

Microprocessors - MPU 8313 REV2.2 PB NO ENC

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Manufacturer

BOSTOCK HK LIMITED

Part Number:

MPC8313ZQADDC

Manufacturer:

Freescale Semiconductor

PCI Bus Interface

Figure 13-27

13.3.3.10 Latency Timer Configuration Register

Figure 13-28

shows the bit settings of the cache line size register.

shows the bit settings of the latency timer register.

Cache Line Size Configuration Register

shows the cache line size fields.

shows the latency timer fields.

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Table 13-31. Cache Line Size Configuration Register Field Descriptions

Table 13-32. Latency Timer Configuration Register Field Descriptions

Latency timer. Specifies a granularity of 8 PCI clocks, the length of time that the PCI controller, when

mastering a transaction, may hold the bus as the result of a bus grant. Refer to the PCI 2.3

specification for the rules by which the PCI controller completes transactions when the timer has

Cache line size. Cache-line in terms of 32-bit words. Although the register is writable, only the value

0x08 is legal.

Figure 13-27. Cache Line Size Configuration Register

Figure 13-28. Latency Timer Configuration Register

Freescale Semiconductor

Access: Read/Write