MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 645

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Figure 14-2
capable of transferring 64-bit words between the bus and any register inside the SEC.
An operation begins when the host writes a descriptor pointer to the fetch FIFO in the SEC channel. From
this point on, the channel directs the sequence of operations. The channel uses the descriptor pointer to
read the descriptor, then decodes the first word of the descriptor to determine the operation to be performed
and the execution units needed to perform it. The channel requests the controller to assign the needed
execution units. Next the channel requests that the controller fetch the keys, IVs and data from locations
specified in the rest of the descriptor. The controller satisfies the requests by making requests to the master
interface per the programmable priority scheme. Data is fed into the execution units through their registers
and the proper input FIFOs. The execution units read from their input FIFOs and write processed data to
their output FIFOs. The channel requests the controller to write data from the output FIFOs and registers
back to system memory through the master/slave interface.
For most packets, the entire payload is too long to fit in the input or output FIFO. The SEC then uses a
flow control scheme for reading and writing data. The channel directs the controller to read bursts of input
as necessary to keep refilling the input FIFO, until the entire payload has been fetched. Similarly, the
channel directs the controller to write bursts of output whenever enough accumulates in the output FIFO.
14.1.1
As a crypto acceleration block, the SEC controller has been designed for easy use and integration with
existing systems and software. All cryptographic functions are accessible through descriptors. A descriptor
specifies a cryptographic function to be performed, and contains pointers to all necessary input data and
to the places where output data is to be written. Some descriptor types perform multiple functions to
facilitate particular protocols. A descriptor is diagrammed in
Freescale Semiconductor
Descriptors
shows a simplified block diagram of the SEC internal architecture. The controller block is
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Controller
Channel
External
Bus
Figure 14-2. SEC Functional Modules
Internal
Bus
AESU
Execution Units (EUs)
FIFO
FIFO
Table
14-1.
DEU
MDEU
FIFO
Security Engine (SEC) 2.2
14-3