MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 484

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
Table 10-25
10.3.1.19 Flash Command Register (FCR)
The local bus Flash command register (FCR), shown in
EEPROM command bytes that may be referenced by opcodes in FIR during FCM operation. The values
of the commands should follow the manufacturer’s datasheet for the relevant NAND Flash device.
10-36
Offset 0x0_50E4
Offset 0x0_50E8
Reset
Reset
modify the contents of any currently unused FCM RAM buffer in preparation for the next operation.
12–15
16–19
20–23
24–27
28–31
8–11
Bits
W
0–3
4–7
W
R
R
0
0
Name
OP0
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
describes FIR fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
CMD0
3
FCM operation codes. OP0 is executed first, followed by OP1, through to OP7.
0000 NOP—No-operation and end of operation sequence
0001 CA—Issue current column address as set in FPAR, with length set by ORx[PGS]
0010 PA—Issue current block+page address as set in FBAR and FPAR, with length set by FMR[AL]
0011 UA—Issue user-defined address byte from next AS field in MDR
0100 CM0—Issue command from FCR[CMD0]
0101 CM1—Issue command from FCR[CMD1]
0110 CM2—Issue command from FCR[CMD2]
0111 CM3—Issue command from FCR[CMD3]
1000 WB—Write FBCR bytes of data from current FCM buffer to Flash device
1001 WS—Write one byte (8b port) of data from next AS field of MDR to Flash device
1010 RB—Read FBCR bytes of data from Flash device into current FCM RAM buffer
1011 RS—Read one byte (8b port) of data from Flash device into next AS field of MDR
1100 CW0—Wait for LFRB to return high or time-out, then issue command from FCR[CMD0]
1101 CW1—Wait for LFRB to return high or time-out, then issue command from FCR[CMD1]
1110 RBW—Wait for LFRB to return high or time-out, then read FBCR bytes of data from Flash device
1111 RSW—Wait for LFRB to return high or time-out, then read one byte (8b port) of data from Flash
4
OP1
into current FCM RAM buffer
device into next AS field of MDR
7
7
8
8
Figure 10-22. Flash Instruction Register
Figure 10-23. Flash Command Register
OP2
Table 10-25. FIR Field Descriptions
11 12
CMD1
OP3
All zeros
All zeros
15 16
15 16
Description
Figure
OP4
10-23, holds up to four NAND Flash
CMD2
19 20
OP5
23 24
23 24
Freescale Semiconductor
OP6
Access: Read/Write
Access: Read/Write
CMD3
27 28
OP7
31
31