MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 346

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

e300 Processor Core Overview
7.3.3
The following sections describe the general cache characteristics as implemented in the PowerPC
architecture and the core implementation.
7.3.3.1
The PowerPC architecture does not define hardware aspects of cache implementations. The e300 core
controls the following memory access modes on a page or block basis:
Note that in the core, a cache block is defined as eight words. The VEA defines cache management
instructions that provide a means by which the application programmer can affect the cache contents.
7.3.3.2
The e300c3 provides 16-Kbyte, four-way set-associative instruction and data caches.The caches are
physically addressed, and the data cache can operate in either write-back or write-through mode as
specified by the PowerPC architecture.
The data cache is configured as 128 sets of 4 blocks each on the e300c3. Each block consists of 32 bytes,
2 state bits, and an address tag. The two state bits implement the three-state MEI
(modified/exclusive/invalid) protocol. Each block contains eight 32-bit words. Note that the PowerPC
architecture defines the term ‘block’ as the cacheable unit. For the core, the block size is equivalent to a
cache line. A block diagram of the data cache organization is shown in
The instruction cache is configured as 128 sets of 4 blocks each on the e300c3. Each block consists of
32 bytes, an address tag, and a valid bit. The instruction cache may not be written to, except through a
block fill operation. In the e300 core, the instruction cache is blocked only until the critical load completes.
The e300 core supports instruction fetching from other instruction cache lines following the forwarding of
the critical-first-double-word of a cache line load operation. Successive instruction fetches from the cache
line being loaded are forwarded, and accesses to other instruction cache lines can proceed during the cache
line load operation. The instruction cache is not snooped, and cache coherency must be maintained by
software. A fast hardware invalidation capability is provided to support cache maintenance.
The e300c3 data cache is configured as 128 sets of four blocks per set. The organization of the data cache
is shown in
7-28
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The core implements the following instruction which is added to support easy start-up initialization
or reloading of the instruction cache.
— Instruction Cache Block Touch (icbt)
The core provides the following performance monitor instructions:
— Move to Performance Monitor Register (mtpmr)
— Move from Performance Monitor Register (mfpmr)
Write-back/write-through mode
Caching-inhibited mode
Memory coherency
Cache Implementation
Figure
PowerPC Cache Characteristics
Implementation-Specific Cache Organization
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
7-3.
Figure
7-3.
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