MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 992

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16-64
13–12
31–30
29–23
22–16
11–8
Bits
Bits
6–0
14
7
Device Address Selects the specific device serving as the data source or sink.
Port Number
Hub Addr
Name
EndPt
Name
EPS
Mult
dtc
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
I
Table 16-58. Endpoint Characteristics: Queue Head DWord 1 (continued)
Data toggle control (DTC). Specifies where the host controller should get the initial data toggle on
an overlay transition.
0 Ignore DT bit from incoming qTD. Host controller preserves DT bit in the queue head.
1 Initial data toggle comes from incoming qTD DT bit. Host controller replaces DT bit in the queue
Endpoint speed. This is the speed of the associated endpoint.
00 Full-speed (12 Mbps)
01 Low-speed (1.5 Mbps)
10 High-speed (480 Mbps)
11 Reserved, should be cleared This field must not be modified by the host controller.
Endpoint number. Selects the particular endpoint number on the device serving as the data source
or sink.
Inactivate on next transaction. This bit is used by system software to request that the host controller
set the Active bit to zero. This field is only valid when the queue head is in the periodic schedule and
the EPS field indicates a full- or low-speed endpoint. Setting this bit when the queue head is in the
asynchronous schedule or the EPS field indicates a high-speed device yields undefined results.
High-bandwidth pipe multiplier. This field is a multiplier used to key the host controller as the number
of successive packets the host controller may submit to the endpoint in the current execution. The
host controller makes the simplifying assumption that software properly initializes this field
(regardless of location of queue head in the schedules or other run time parameters).
00 Reserved, should be cleared. A zero in this field yields undefined results.
01 One transaction to be issued for this endpoint per micro-frame
10 Two transactions to be issued for this endpoint per micro-frame
11 Three transactions to be issued for this endpoint per micro-frame
This field is ignored by the host controller unless the EPS field indicates a full- or low-speed device.
The value is the port number identifier on the USB 2.0 hub (for hub at device address Hub Addr
below), below which the full- or low-speed device associated with this endpoint is attached. This
information is used in the split-transaction protocol.
This field is ignored by the host controller unless the EPS field indicates a full-or low-speed device.
The value is the USB device address of the USB 2.0 hub below which the full- or low-speed device
associated with this endpoint is attached. This field is used in the split-transaction protocol.
Table 16-59. Endpoint Capabilities: Queue Head DWord 2
head from the DT bit in the qTD.
Description
Description
Freescale Semiconductor