MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 913

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register #1 to set up the interface mode
Set up the MII Mgmt for a write cycle to the external PHY Mode control register to set up the interface mode selection.
Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),
If auto-negotiation was enabled in the PHY, check to see if PHY has completed Auto-Negotiation.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x00.
(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
Table 15-167. MII Mode Register Initialization Steps (continued)
read the MIIMSTAT register and check bit 10 (AN Done and Link is up)
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0100]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_00uu_00uu_0u00_0000]
MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111]
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0001]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Check auto-negotiation attributes in the PHY as necessary.
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
where u is user defined based on desired configuration.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete
Check to see if MII Mgmt write is complete
Initialize MACnADDR1/2 (Optional)
Clear MIIMCOM[Read Cycle].
Initialize GADDR n (Optional)
Set MIIMCOM[Read Cycle].
Initialize RCTRL (Optional)
When MIIMIND[BUSY]=0,
Initialize IMASK (Optional)
Clear IEVENT register,
selection.
Enhanced Three-Speed Ethernet Controllers
15-195