MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 775

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.3.8
RQFPR (see
filer table. The table entries are described in greater detail in
word accessed through RQFPR is defined by the current value of RQFAR.
describe the fields of the RQFPR register according to property ID.
Freescale Semiconductor
25–26
28–31
Bit
22
23
24
27
Offset eTSEC1:0x2_433C; eTSEC2:0x2_533C;
Reset
W
R
Name
CMP
AND
CLE
REJ
PID
0
—
Figure
Figure 15-29. Receive Queue Filer Table Property IDs 0, 2–15 Register Definition
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Receive Queue Filer Table Property Register (RQFPR)
Cluster entry/exit (used in combination with AND bit). This bit brackets clusters, marking the start and end
entries of a cluster. Clusters cannot be nested.
0 Regular RQCTRL entry.
1 If entry matches and AND = 1, treat subsequent entries as belonging to a nested cluster and enter the
Reject frame. This bit and its specified action are ignored if AND = 1.
0 If entry matches, accept frame and file it to RxBD ring Q.
1 If entry matches, reject frame and discard it, ignoring Q.
Match this entry and the next entry as a pair.
0 Match property[PID] against RQPROP, independent of the next entry.
1 Match property[PID] against RQPROP. If matched and CLE = 0, attempt to match next entry, otherwise,
Comparison operation to perform on the RQPROP entry at this index when PID > 0. The property value
extracted by the frame parser is masked by the 32-bit mask_register prior to comparison against RQPROP.
However, the property value is not permanently altered by the value in mask_register . By default,
mask_register is initialized to 0xFFFF_FFFF before each frame is processed.
In the case where PID = 0, CMP is interpreted as follows:
00/01 Filer mask_register is set to all 32 bits of RQPROP, and this entry always matches .
10/11 Filer mask_register is set to all 32 bits of RQPROP, and this entry always fails to match .
In the case where PID > 0, CMP is interpreted as follows (& is bit-wise AND operator):
00 property [PID] & mask_register = RQPROP
01 property [PID] & mask_register >= RQPROP
10 property [PID] & mask_register != RQPROP
11 property [PID] & mask_register < RQPROP
Reserved, should be written with zero.
Property identifier. The value in the RQPROP entry at this index is interpreted according to PID (see
Table
cluster; otherwise skip all entries up to and including the next cluster exit. If AND = 0, exit current cluster.
skip all entries up to and including the entry with AND = 0. If matched and CLE = 1, enter cluster of entries,
otherwise, skip all entries up to and including the entry with CLE = 1 (cluster exit).
15-29) is accessed to read or write the RQPROP words in entries of the receive queue
15-34).
Table 15-33. RQFCR Field Descriptions (continued)
(undefined)
RQPROP
Description
Section 15.6.4.2, “Receive Queue Filer.”
Enhanced Three-Speed Ethernet Controllers
Figure 15-29
and
Access: Read/Write
Figure 15-30
15-57
The
31