MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 203

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.5.1.7
RCER, shown in
RCR.
Table 4-32
4.5.2
The clock configuration and status registers are shown in
4.5.2.1
SPMR is shown in
input signal and the reset configuration word low loaded during the reset flow. Note that this register is
updated only during a power-on reset sequence and not by a hard reset sequence. It may hold values
different than those in the RCWLR after a a hard reset sequence.
Freescale Semiconductor
Address 0x0_0920
0–30
0x0_0A0C–
Bits
0x0_0AFC
0x0_0A00
0x0_0A04
0x0_0A08
Reset
Reset
31
Address
W
W
R
R
Name
CRE
16
—
0
defines the bit fields of RCER.
Clock Configuration Registers
Reset Control Enable Register (RCER)
System PLL Mode Register (SPMR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
System PLL mode register (SPMR)
Output clock control register (OCCR)
System clock control register (SCCR)
Reserved, should be cleared
Reserved, should be cleared.
Control register enabled. When set, indicates that the RPR was accessed with a value that enables the RCR.
Writing 1 to this bit disables the RCR and clears this bit. Writing zero has no effect.
Figure
Figure
4-12, indicates by the CRE field that the RPR is accessed with a value that enables
Table 4-33. Clock Configuration Registers Memory Map
4-13, gets its values according to the CFG_CLKIN_DIV reset configuration
Figure 4-12. Reset Control Enable Register (RCER)
Register
Table 4-32. RCER Bit Settings
—
All zeros
All zeros
Description
—
Table
Access
4-33.
R/W
R/W
—
R
0x7DDF_FFFF
0x0000_80C0
0x nnnn _ nnnn
Reset
Reset, Clocking, and Initialization
—
Access: User read/write
29
Section/Page
4.5.2.1/4-37
4.5.2.2/4-39
4.5.2.3/4-40
30
—
CRE
15
31
4-37