MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 480

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
Table 10-22
10-32
11–15
16–23
24–27
28–31 BMTPS Bus monitor timer prescale. Defines the multiplier, PS, to scale LBCR[BMT] for determining bus
Bits
1–7
8–9
10
0
BCTLC Defines the use of LBCTL
Name
LDIS
AHD
BMT
describes LBCR fields.
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MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Local bus disable
0 Local bus is enabled.
1 Local bus is disabled. No internal transactions will be acknowledged.
Reserved
00 LBCTL is used as W/R control for GPCM or UPM accesses (buffer control).
01 LBCTL is used as LOE for GPCM accesses only.
10 LBCTL is used as LWE for GPCM accesses only.
11 Reserved.
Address hold disable. Removes part of the hold time for LAD with respect to LALE in order to lengthen
the LALE pulse.
0 During address phases on the local bus, the LALE signal negates 2 platform clock period prior to
1 During address phases on the local bus, the LALE signal negates 1 platform clock period prior to
Reserved. Reads to bit 13 return 1.
Bus monitor timing. Defines the bus monitor time-out period. Clearing BMT (reset value) selects the
maximum count of bus clock cycles. For non-zero values of BMT, the number of LCLK clock cycles to
count down before a time-out error is generated is given by:
bus cycles = BMT × PS, where PS is set according to LBCR[BMTPS].
The value of BMT × PS must not be less than 40 bus cycles for reliable operation.
Reserved
time-outs.
0000 PS = 8
0001 PS = 16
0010 PS = 32
0011 PS = 64
0100 PS = 128
0101 PS = 256
0110 PS = 512
0111 PS = 1024
1000 PS = 2048
1001 PS = 4096
1010 PS = 8192
1011 PS = 16,384
1100 PS = 32,768
1101 PS = 65,536
1110 PS = 131,072
1111 PS = 262,144
the address being invalidated. At 66.6 MHz, this provides 3 ns of address hold time at the external
address latch.
the address being invalidated. This halves the address hold time, but extends the latch enable
duration. This may be necessary for very high frequency designs.
Table 10-22. LBCR Field Descriptions
Description
Freescale Semiconductor