MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1074

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
By reading the status fields of the completed dTDs, the DCD can determine if the transfers completed
successfully. Success is determined with the following combination of status bits:
Should any combination other than the one shown above exist, the DCD must take proper action. Transfer
failure mechanisms are indicated in the Device Error Matrix.
In addition to checking the status bit the DCD must read the Transfer Bytes field to determine the actual
bytes transferred. When a transfer is complete, the Total Bytes transferred is by decremented by the actual
bytes transferred. For Transmit packets, a packet is only complete after the actual bytes reaches zero, but
for receive packets, the host may send fewer bytes in the transfer according the USB variable length packet
protocol.
16.8.5.5
It is necessary for the DCD to flush to de-prime one more endpoints on a USB device reset or during a
broken control transfer. There may also be application specific requirements to stop transfers in progress.
The following procedure can be used by the DCD to stop a transfer in progress:
16.8.5.6
The following table summarizes packet errors that are not automatically handled by the USB_DR
16-146
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•
•
•
1. Write a ‘1’ to the corresponding bit(s) in ENDPTFLUSH.
2. Wait until all bits in ENDPTFLUSH are ‘0’.
3. Software note: this operation may take a large amount of time depending on the USB bus activity.
4. Read ENDPTSTATUS to ensure that for all endpoints commanded to be flushed, that the
Active = 0
Halted = 0
Transaction Error = 0
Data Buffer Error = 0
It is not desirable to have this wait loop within an interrupt service routine.
corresponding bits are now ‘0’’ If the corresponding bits are ‘1’ after step #2 has finished, then the
flush failed as described in the following:
Explanation: In very rare cases, a packet is in progress to the particular endpoint when commanded
flush using ENDPTFLUSH. A safeguard is in place to refuse the flush to ensure that the packet in
progress completes successfully. The DCD may need to repeatedly flush any endpoints that fail to
flush be repeating steps 1–3 until each endpoint is successfully flushed.
Flushing/De-Priming an Endpoint
Device Error Matrix
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Overflow **
ISO Packet Error
ISO Fulfillment Error
Error
Table 16-91. Device Error Matrix
Direction
Both
RX
RX
Packet
Type
Any
ISO
ISO
Error Bit
Buffer
Data
0
0
1
Transaction
Error Bit
0
1
1
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