MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 172

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
4.2.2
Assertion of the PORESET external signal initiates the power-on reset flow. PORESET should be asserted
externally for at least 32 input clock cycles after stable external power to the device is applied.
Directly after the negation of PORESET, the device starts the configuration process. The device asserts
HRESET throughout the power-on reset process, including configuration. Configuration time varies
according to the configuration source and SYS_CLK_IN (PCI host mode) or PCI_CLK (PCI agent mode)
frequency. Initially, the reset configuration inputs are sampled to determine the configuration source and
the input clock division mode. Next, the device starts loading the reset configuration words. The system
PLL begins to lock according to the clock mode values in the reset configuration word low. When the
system PLL is locked, the clock unit starts distributing clock signals in the device. At this stage, the core
PLL begins to lock. When it is locked and the reset configuration words are loaded, HRESET is released.
The detailed power-on reset (POR) flow for the device is as follows:
4-6
Resets:
PLLs, clocks, RTC unit, and error
capture registers
Resets:
DDR, LBC, I/O multiplexors, GTM,
PIT, GPIO, system configuration,
and local access windows
Resets other internal logic
Reset configuration words loaded
HRESET driven
Hard reset to e300 core
High priority interrupt to the e300
core
1. Power is applied to meet the specifications in the device data sheet.
2. The system asserts PORESET and TRST, causing all registers to be initialized to their default states
3. The system applies a stable SYS_CLK_IN (PCI host mode) or PCI_CLK (PCI agent mode) signal
4. The system negates PORESET after at least 32 stable SYS_CLK_IN (PCI host mode) or PCI_CLK
and most I/O drivers to be released to high-impedance.
Some clock, clock enabled, and system control signals remain active.
and stable reset configuration inputs (CFG_RESET_SOURCE, CFG_CLKIN_DIV).
(PCI agent mode) clock cycles.
Power-On Reset Flow
Action
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Power-On Reset
Yes
Yes
Yes
Yes
Yes
Yes
No
Table 4-4. Reset Actions
Software Hard Reset
External Hard Reset
Software Watchdog
Bus Monitor
Checkstop
Yes
Yes
Yes
Yes
Yes
No
No
Reset Source
JTAG Reset
Yes
Yes
No
No
No
No
No
Freescale Semiconductor
External Soft
Reset
Yes
Yes
No
No
No
No
No