MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 764

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
TRANSMIT command is issued and the frame completes its transmission) in order to change the next
TxBD eTSEC transmits.
Table 15-23
15.5.3.2.10 Transmit Descriptor Base Address Registers (TBASE0–TBASE7)
The TBASEn registers are written by the user with the base address of each TxBD ring n. Each such value
must be divisible by eight, since the three least significant bits always write as 000.
the definition for the TBASEn registers.
Table 15-24
15-46
29–31
29–31
0–28 TBASE n Transmit base for ring n . TBASE defines the starting location in the memory map for the eTSEC TxBDs. This
Bits
0–28
Bits
Offset eTSEC1:0x2_4184+8× n ; eTSEC2:0x2_5184+8× n
Reset
Offset eTSEC1:0x2_4204+8× n ; eTSEC2:0x2_5204+8× n
Reset
W
W
R
R
Name
TBPTR n Current TxBD pointer for TxBD ring n . Points to the current BD being processed or to the next BD the
Name
—
0
0
—
describes the fields of the TBPTRn register.
describes the fields of the TBASEn registers.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how many
BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the eTSEC transmit
function on the associated ring.
Reserved
transmitter uses when it is idling. When the end of the TxBD ring is reached, eTSEC initializes TBPTR n to
the value in the corresponding TBASE n . The TBPTR register is internally written by the eTSEC’s DMA
controller during transmission. The pointer increments by eight (bytes) each time a descriptor is closed
successfully by the eTSEC. Note that the three least significant bits of this register are read-only and zero.
After an error condition, the eTSEC returns TBPTR n to point to the first BD of the frame partially transmitted.
Reserved
Figure 15-18. TBPTR0–TBPTR7 Register Definition
Table 15-24. TBASE0–TBASE7 Field Descriptions
Figure 15-19. TBASE Register Definition
Table 15-23. TBPTR n Field Descriptions
TBPTR n
TBASE n
All zeros
All zeros
Description
Description
Figure 15-19
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
28 29
28 29
describes
—
—
31
31