MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 255

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.6.5.3
The periodic interval timer prescale register (PTPSR), shown in
used to configure the PIT prescaler’s value.
Table 5-51
5.6.5.4
The periodic interval timer counter register (PTCTR), shown in
shows the current value in the PIT counter. The PTCTR counter is not affected by reads or writes.
Table 5-52
5.6.5.5
The periodic interval timer event register (PTEVR), shown in
the interrupts. The register can be read at any time.
PTEVR bits are cleared by writing ones. Writing zeros does not affect the value of the status bits.
Freescale Semiconductor
0–31
0–31
Offset 0x08
Offset 0x0C
Reset
Reset
Bits
Bits
W
W
R
R
0
0
Name
PRSC PIT prescaler bits. Selects the input clock divider to generate the PIT counter clock. The prescaler is
Name
CNTV PIT counter value field. Contains the current value of the time counter. This is a read-only field. Writes have
defines the bit fields of PTPSR.
defines the bit fields of PTCTR.
Periodic Interval Timer Prescale Register (PTPSR)
Periodic Interval Timer Counter Register (PTCTR)
Periodic Interval Timer Event Register (PTEVR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
programmed to divide the PIT clock input by values from 1 to 4,294,967,296. The value 0x0000 divides the
clock by 1 and 0xFFFF_FFFF divides the clock by 4,294,967,296.
To accurately predict the timing of the next count, change the PRSC bit only when the enable bit PTCNR[CLE]
is clear. Changing PRSC resets the prescaler counter. System reset and the loading of a new value into the
counter also reset the prescaler counter. Clearing the PTCNR[CLE] bit stops the prescaler counter.
no effect on PTCTR[CNTV].
Figure 5-35. Periodic Interval Timer Prescale Register (PTPSR)
Figure 5-36. Periodic Interval Timer Counter Register (PTCTR)
Table 5-51. PTPSR Bit Settings
Table 5-52. PTCTR Bit Settings
All zeros
All zeros
PRSC
CNTV
Description
Description
Figure
Figure
Figure
5-37, is used to report the source of
5-36, is a read-only register that
5-35, is a read/write register that
System Configuration
Access: Read/Write
Access: Read only
5-47
31
31