MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 617

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 13-35
13.3.3.16 GPL Extended Base Address Registers 1–2
Two general-purpose local access base address registers are provided to allow access to local memory
space. These registers are closely tied to PIBARn, PIEBARn, and PIWARn in the CSR memory space. A
write to a GPL extended base address register also causes a change in the base address bits that are not
masked according to the IWS field of PIWARx in the corresponding PIBARn/PIEBARn. Note that this
write operation does not change bits that are masked by the IWS field. For read operations these masked
bits will always return zeros.
Figure 13-34
Table 13-36
Freescale Semiconductor
Offset 0x18, 0x20
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Offset 0x1C, 0x24
Reset
31–12
11–4
W
Bits
2–1
31–0
Bits
R
3
0
W
R
31
31
shows the bit settings of the GPL base address register 1–2.
shows the bit settings of the GPL extended base address register 1–2.
shows the GPL extended base address registers 1–2 fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Name
Name
PRE
MSI
EBA
BA
—
Table 13-36. GPL Extended Base Address Registers 1–2 Field Descriptions
T
Table 13-35. GPL Base Address Register 1,2 Field Descriptions
Base address. Defines the two portion of the base address for the inbound window. Bits 11–4 are
hard-wired to 0 since the minimum window size is 4 Kbytes.
Reserved
Prefetchable. This bit is read-only and contains the value of the PF bit in PIWAR n .
Type. Hard-wired to 10.
Memory space indicator. Hard-wired to 0.
Extended base address. Defines the high portion of the base address for the inbound window.
Figure 13-34. GPL Extended Base Address Registers 1–2
Figure 13-33. GPL Base Address Registers 1–2
BA
All zeros
EBA
Description
Description
12 11
—
4
Access: Read/Write
Access: Read/Write
PRE
0
3
PCI Bus Interface
1
2
T
0
1
13-35
MSI
0
0
0