MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 473

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x0_50B0
Table 10-15
10.3.1.9
The transfer error status register (LTESR) indicates the cause of an error or event. LTESR, shown in
Figure
can clear but not set bits. A bit is cleared whenever the register is written, and the data in the corresponding
bit location is a 1. For example, to clear only the write protect error bit (LTESR[WP]) without affecting
other LTESR bits, 0x0400_0000 should be written to the register. After any error/event reported by
LTESR, LTEATR[V] must be cleared for LTESR to updated again.
Reset
Reset
Freescale Semiconductor
8–31
Bits
0–7
W
W
R
R
BM
10-13, is a write-1-to-clear register. Reading LTESR occurs normally; however, write operations
16
0
Name
LURT UPM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period according
—
FCT
describes LURT fields.
Transfer Error Status Register (LTESR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
1
to the following equation:
Example: For a 266-MHz system clock and a required service rate of 15.6 µs, given MRTPR[PTP] = 32, the
LURT value should be 128 decimal. 128/(266 MHz/32) = 15.4 µs, which is less than the required service
period of 15.6 µs.
Note that the reset value (0x00) sets the maximum period to 256 x MRTPR[PTP] system clock cycles.
Reserved
PAR
2
3
Figure 10-13. Transfer Error Status Register (LTESR)
—
4
Table 10-15. LURT Field Descriptions
WP
5
6
TimerPeriod
—
—
7
All zeros
All zeros
ATMW ATMR
Description
8
=
--------------------------------------------- -
⎛
⎝
Fsystemclock
--------------------------------------- -
MRTPR PTP
9
LURT
[
10
—
]
11
⎞
⎠
CS
12
Enhanced Local Bus Controller
13
29
UCC
—
30
Access: w1c
10-25
CC
15
31