MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1063

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

To prevent the USB_DR from re-sending the same packet, the device controller will respond to the error
packet by acknowledging it with either an ACK or NYET response.
16.8.3.3
All transactions on the USB bus are initiated by the host and in turn, the device must respond to any request
from the host within the turnaround time stated in the Universal Serial Bus Revision 2.0 Specification.
A USB host will send requests to the USB_DR in an order that can not be precisely predicted as a single
pipeline, so it is not possible to prepare a single packet for the device controller to execute. However, the
order of packet requests is predictable when the endpoint number and direction is considered. For example,
if endpoint 2 (transmit direction) is configured as a bulk pipe, then we can expect the host will send IN
requests to that endpoint. This USB_DR prepares packets for each endpoint/direction in anticipation of the
host request. The process of preparing the device controller to send or receive data in response to host
initiated transaction on the bus is referred to as ‘priming’ the endpoint. This term will be used throughout
the following documentation to describe the USB_DR operation so the DCD can be architected properly
use priming. Further, note that the term ‘flushing’ is used to describe the action of clearing a packet that
was queued for execution.
16.8.3.3.1
Priming a transmit endpoint will cause the device controller to fetch the device transfer descriptor (dTD)
for the transaction pointed to by the device queue head (dQH). After the dTD is fetched, it will be stored
in the dQH until the device controller completes the transfer described by the dTD. Storing the dTD in the
dQH allows the device controller to fetch the operating context needed to handle a request from the host
without the need to follow the linked list, starting at the dQH when the host request is received.
After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device
controller. This FIFO is split into virtual channels so that the leading data can be stored for any endpoint
up to the maximum number of endpoints configured at device synthesis time.
After a priming request is complete, an endpoint state of primed is indicated in the ENDPTSTATUS
register. For a primed transmit endpoint, the device controller can respond to an IN request from the host
and meet the stringent bus turnaround time of High Speed USB.
Since only the leading data is stored in the device controller FIFO, it is necessary for the device controller
to begin filling in behind leading data after the transaction starts. The FIFO must be sized to account for
the maximum latency that can be incurred by the system memory bus.
16.8.3.3.2
Priming receive endpoints is identical to priming of transmit endpoints from the point of view of the DCD.
At the device controller the major difference in the operational model is that there is no data movement of
the leading packet data simply because the data is to be received from the host.
Note as part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels
like the transmit FIFO. Thus, the size of the RX FIFO does not scale with the number of endpoints.
Freescale Semiconductor
Device Operational Model For Packet Transfers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Priming Transmit Endpoints
Priming Receive Endpoints
Universal Serial Bus Interface
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