MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 239

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Offset 0x4
1
5.4.4
The WDT programmable register map occupies 16 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All WDT registers are 16- or 32-bits wide, located on 16-bit address boundaries, and should be accessed
as 16- or 32-bit quantities. All addresses used in this chapter are offsets from the WDT base, as defined in
Chapter 2, “Memory Map.”
Table 5-33
1
5.4.4.1
The system watchdog control register (SWCRR), shown in
period and configures watchdog timer operation. SWCRR can be read at any time but can be written only
once after system reset.
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Freescale Semiconductor
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
0xC–0xD
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
0x0–0x3
Offset
W
R
0xE
0x4
0x8
0
shows the WDT memory map.
WDT Memory Map/Register Definition
Reserved
System watchdog control register (SWCRR)
System watchdog count register (SWCNR)
Reserved
System watchdog service register (SWSRR)
System Watchdog Control Register (SWCRR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 5-19. System Watchdog Control Register (SWCRR)
SWTC
Table 5-33. WDT Register Address Map
Register
15 16
Figure
Access
5-19, controls the software watchdog
R/W
R/W
—
—
—
R
or 0xFFFF_0007
0xFFFF_0003
0x0000_FFFF
Reset Value
0x0000
—
—
28
SWEN SWRI SWPR
System Configuration
1
Access: Read/Write
0
29
1
Section/ Page
5.4.4.1/5-31
5.4.4.2/5-32
5.4.4.3/5-33
30
1
—
—
5-31
31
1