MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 797

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 15-52
15.5.3.5.16 MAC Exact Match Address 1–15 Part 2 Registers
The MAC01ADDR2–MAC15ADDR2 registers are written by the user with the unicast or multicast
addresses aliasing the MAC.
registers.
Table 15-53
15.5.3.6
This section describes the MIB registers. The eTSEC RMON module has 37 separate statistics counters,
which simply count or accumulate statistical events that occur as packets transmitted and received. These
counters support RMON MIB group 1, RMON MIB group 2 if table counters, RMON MIB group 3,
RMON MIB group 9, RMON MIB 2, and the IEEE 802.3 Ethernet MIB.
Freescale Semiconductor
Offset eTSEC1:0x2_454C+8× n ; eTSEC2:0x2_554C+8× n
Reset
W
16–31
R
8–15 Exact Match Address, 1st Octet
16–23 Exact Match Address, 4th Octet Holds the fourth octet of the exact match address. The fourth octet
24–31 Exact Match Address, 3rd Octet Holds the third octet of the exact match address. The third octet
8–15 Exact Match Address, 5th Octet Holds the fifth octet of the exact match address. The fifth octet
0–7
Bit
0–7
Bit
0
Exact Match Address,
Exact Match Address, 2nd Octet
describes the fields of a MACnADDR1 register.
describes the fields of a MACxADDR2 register.
Exact Match Address, 6th Octet Holds the sixth octet of the exact match address. The sixth octet
MIB Registers
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
(MAC01ADDR2–MAC15ADDR2)
2nd Octet
Figure 15-51. MAC Exact Match Address x Part 2 Register Definition
Table 15-55. MAC01ADDR2–MAC15ADDR2 Field Descriptions
Name
Name
—
Figure 15-51
Table 15-54. MAC n ADDR1 Field Descriptions
7
8
Exact Match Address,
(destination address bits 40
(destination address bits 32
(destination address bits 24
(destination address bits 16
1st Octet
This field holds the second octet of the exact match address. The
second octet (destination address bits 8–15) defaults to a value of
0x0.
This field holds the first octet of the exact match address. The first
octet (destination address bits 0–7) defaults to a value of 0x0.
Reserved
describes the definition for all of the fifteen MACxADDR2
All zeros
15 16
–
–
–
–
Description
47) defaults to a value of 0x0.
39) defaults to a value of 0x0.
31) defaults to a value of 0x0.
23) defaults to a value of 0x0.
Description
Enhanced Three-Speed Ethernet Controllers
—
Access: Read/Write
15-79
31