MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 876

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
The receive timer threshold counter is reset to the value in RXIC[ICTT] and begins counting down on
receiving the frame following an interrupt.
15.6.2.11 Inter-Frame Gap Time
If a station must transmit, it waits until the LAN becomes silent for a specified period (inter-frame gap, or
IFG). The minimum inter-packet gap (IPG) time for back-to-back transmission is set by
IPGIFG[Back-to-Back Inter-Packet-Gap]. The receiver receives back-to-back frames with the minimum
interframe gap (IFG) as set in IPGIFG[Minimum IFG Enforcement]. If multiple frames are ready to
transmit, the Ethernet controller follows the minimum IPG as long as the following restrictions are met:
If the first TxBD alignment restriction is not met, the back-to-back IPG may be as many as 32 cycles. If
the TxBD size restriction is not met, the back-to-back IPG may be significantly longer.
In half-duplex mode, after a station begins sending, it continually checks for collisions on the LAN. If a
collision is detected, the station forces a jam signal (all ones) on its frame and stops transmitting. Collisions
usually occur close to the beginning of a packet. The station then waits a random time period (back-off)
before attempting to send again. After the back-off completes, the station waits for silence on the LAN
(carrier sense negated) and then begins retransmission (retry) on the LAN. Retransmission begins 36 bit
times after carrier sense is negated for at least 60 bit times. If the frame is not successfully sent within a
specified number of retries, an error is indicated (collision retry limit exceeded).
15.6.2.12 Internal and External Loop Back
Setting MACCFG1[Loop Back] causes the MAC transmit outputs to be looped back to the MAC receive
inputs. Clearing this bit results in normal operation. This bit is cleared by default. Clearing this bit results
in normal operation.
15.6.2.13 Error-Handling Procedure
The eTSEC reports frame reception and transmission error conditions using the channel BDs, the error
counters, and the IEVENT register.
Transmission errors are described in
15-158
Transmitter underrun
Retransmission
attempts limit expired
•
•
The first TxBD pointer, TBPTRn, of any given frame is located at a 16-byte aligned address.
Each TxBD[Data Length] is greater-than or equal to 64 bytes.
Error
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Transmitter underrun can occur either after frame transmission has commenced, or in response to an
incomplete sequence of TxBDs. In the former case, the controller sends 32 bits that ensure a CRC
error, and terminates buffer transmission. In the latter case, the relevant transmit queue is halted. In
all cases, the eTSEC closes the buffer, sets TxBD[UN], IEVENT[XFUN], and IEVENT[TXE]. The
controller resumes transmission after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).
The controller terminates buffer transmission, sets TxBD[RL], closes the buffer, IEVENT[CRL], and
IEVENT[TXE]. Transmission resumes after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).
Table 15-150. Transmission Errors
Table
15-150.
Response
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