MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 593

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

13.3
The PCI controller has the following types of registers:
Freescale Semiconductor
•
•
•
PCI_TRDY
Offset
Signal
0x0
0x4
0x8
The PCI configuration access registers. Used for generating PCI configuration accesses from the
CSB. These registers, listed in
the IMMR window.
The PCI memory-mapped registers. Used to manage error functions, general control and status,
and address translation control for the inbound path. These registers are shown in
can be accessed by PCI masters via the PCI controller to the CSB through the PIMMR inbound
window. Note that
contained in the I/O sequencer (IOS) memory-mapped registers.
“DMA/Messaging Unit,”
The PCI configuration space registers. Defined by the PCI specification. These registers are
accessed by PCI masters using configuration accesses and are described in
Configuration Space Registers.”
Memory Map/Register Definitions
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCI_CONFIG_ADDRESS
PCI_CONFIG_DATA
PCI_INT_ACK
Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI target ready.
O
I
Outputs for the bi-directional target ready.
Inputs for the bi-directional target ready.
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
State
State
Table 13-5
Table 13-4. PCI Configuration Access Registers
Asserted—The PCI controller, acting as a PCI target, can complete the current data
Negated—The PCI initiator needs to wait before this PCI controller, acting as a PCI target,
Asserted—Another PCI target is able to complete the current data phase of a transaction.
Negated—A wait cycle from another target.
for more information.
Register
phase of a PCI transaction. During a read, this PCI controller asserts PCI_TRDY to
indicate that valid data is present on PCI_AD[31:0]. During a write, this PCI
controller asserts PCI_TRDY to indicate that it is prepared to accept data.
can complete the current data phase. During a read, this PCI controller negates
PCI_TRDY to insert a wait cycle when it cannot provide valid data to the initiator.
During a write, this PCI controller negates PCI_TRDY to insert a wait cycle when it
cannot accept data from the initiator.
PCI Configuration Access Registers
does not list outbound address translation registers; these are
Table
13-4, are memory-mapped on the CSB and accessed through
Description
Access
R/W
W
R
SeeChapter 12,
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Section 13.3.3, “PCI
Table
13.3.1.1/13-13
13.3.1.2/13-14
13.3.1.3/13-15
Section/Page
PCI Bus Interface
13-5. They
13-11