MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 692

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
14.4.3.9.1
Within the Context register, for use in CBC mode, are two 64-bit context data registers that allow the host
to read/write the contents of the initialization vector (IV):
The IV must be written prior to the message data. If the IV registers are written during message processing,
or the CBC mode bit is not set, a context error will be generated.
The IV registers may only be read after processing has completed, as indicated by the assertion of Interrupt
Done DONE in the AESU status register as shown in
(AESUSR).”
generated.
The IV registers must be read when changing context and restored to resume processing an interrupted
message (CBC mode only).
14.4.3.9.2
In counter mode, a random 128-bit initial counter value is incremented modulo 2
processed. The running counter is encrypted and eXclusive-ORed with the plaintext to derive the
ciphertext, or with the ciphertext to recover the plaintext. The modulus exponent M can be set between 8
and 128 in multiples of 8. The value of M is specified by writing to context register 3 as described in
Figure
14.4.3.9.3
As was noted in the AESU mode register, SRT is not a new AES mode, it is an AESU method of
performing AES-CTR mode with reduced context loading overhead specifically for performing SRTP. It
should be used with descriptor type 0010_0 ‘srtp’. As with counter mode, a random 128-bit initial counter
value is incremented modulo 2
eXclusive-ORed with the plaintext to derive the ciphertext, or with the ciphertext to recover the plaintext.
The modulus exponent M can be set between 8 and 128 in multiples of 8. The value of M is specified by
writing to context register 3 as described in
The only difference between SRT mode and CTR mode is in SRT mode, the AES Context is loaded and
read through context registers 1–3, with no requirement to access context registers 4–7. In CTR mode,
context registers 1–4 must be loaded with zeros, with the Counter and Modulus being loaded into and read
from context registers 5–7.
14.4.3.9.4
The SEC AESU is capable of performing single pass encryption and MAC generation. The host is required
to order the CCM context is such a way that the context can be fetched as a contiguous string into the
context registers, prior to encryption/MAC generation or decryption/MAC validation. The context register
contents for CCM mode is summarized in
14-50
•
•
14-34.
IV1 holds the least significant bytes of the initialization vector (bytes 1–8).
IV2 holds the most significant bytes of the initialization vector (bytes 9–16).
If the IV registers are read prior to assertion of Interrupt Done, an early read error will be
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Context for CBC Mode
Context for Counter Mode
Context for SRT Mode
Context for CCM Mode
M
with each block processed. The running counter is encrypted and
Figure 14-35
Figure
14-34.
Section 14.4.3.5, “AESU Status Register
and further described below.
M
with each block
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