MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 558

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Sequencer
11.4.5
DTCR configures the discard timer, which is used to place a time limit on PCI delayed read transactions
from non-prefetchable memory. Although prefetched reads may be discarded whenever the IOS is full and
needs to allocate another buffer, other delayed reads must not be discarded until the originator actually
receives the data. The DTCR is used to release stuck buffers in case of malfunctioning or disconnected
masters that never come back to read the data they requested
Figure 11-6
Table 11-6
11.5
The IOS is a four-port switch with buffering. Each port has master and slave interfaces. When a port
masters a transaction, the transaction attributes are stored in a buffer and the IOS generates a transaction
to the slave interface of the destination port. The data is also buffered between the ports. The IOS contains
8 cache line (32-byte) transaction buffers, some of which are reserved for specific types of transactions.
The address and data phases of the transactions are independent. The data phases of the transactions are
not required to be in order.
11.5.1
Although the ports use a similar interface, the I/O sequencer is not actually symmetrical. The transaction
forwarding from each source is explained in the following sections.
11-6
Offset 0xF8
Reset
8–31
Bits
1–7
0
W
R
EN
0
Name
PTV
Functional Description
EN
—
1
describes DTCR fields.
Discard Timer Control Register (DTCR)
Transaction Forwarding
shows the DTCR register fields.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Enable. This bit enables the discard timer.
0 Disabled
1 Enabled
Reserved
Preload timer value (PTV). This field contains the preload value for the discard timer. PCI delayed reads from
non-prefetchable address space are discarded after (2
repeated the transaction. 0xFFFFFF is not valid for PTV. For example, to discard a delayed completion if the
PCI master has not repeated the transaction in 2
• Assuming the internal frequency is twice the PCI frequency
• The PTV should equal 2
—
Figure 11-6. Discard Timer Control Register (DTCR)
7
8
Table 11-6. DTCR Field Descriptions
24
– 2
16
(0xFF0000).
All zeros
Description
15
PCI clocks,
24
– PTV) internal clock cycles if the master has not
PTV
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Access: Read/Write
31