MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 667

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

14.4.1.7
The DEU interrupt control register (DEUICR), shown in
errors. For a given error (as defined in
the corresponding bit in the DEUICR is set, the error is ignored; no bit is set in the DEUISR, and no error
interrupt occurs. If the corresponding bit is not set, then upon detection of an error, the DEUISR is updated
to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt
processing.
Freescale Semiconductor
Bits
55
56
57
58
59
60
61
62
63
Name
OFO
DSE
OFE
OFU
IFO
ME
IFE
IFU
AE
DEU Interrupt Control Register (DEUICR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Data size error (DSE): A value was written to the DEU data size register that is not a multiple of 64 bits.
0 No error detected
1 Data size error
Mode error. An illegal value was detected in the mode register. Note: writing to reserved bits in mode
register is likely source of error.
0 No error detected
1 Mode error
Address error. An illegal read or write address was detected within the DEU address space.
0 No error detected
1 Address error
Output FIFO error. The DEU output FIFO was detected non-empty upon write of DEU data size register.
0 No error detected
1 Output FIFO non-empty error
Input FIFO error. The DEU input FIFO was detected non-empty upon generation of DONE interrupt.
0 No error detected
1 Input FIFO non-empty error
Input FIFO underflow. The DEU input FIFO has been read while empty.
0 No error detected
1 Input FIFO has had underflow error
Input FIFO overflow. The DEU input FIFO has been pushed while full.
0 No error detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow control, and FIFO size
Output FIFO underflow. The DEU output FIFO has been read while empty.
0 No error detected
1 Output FIFO has underflow error
Output FIFO overflow. The DEU output FIFO has been pushed while full.
0 No error detected
1 Output FIFO has overflowed
is not a limit to data input. When operated through host-controlled access, the DEU cannot accept
FIFO inputs larger than 256 bytes without overflowing.
Table 14-15. DEUISR Field Descriptions (continued)
Section 14.4.1.6, “DEU Interrupt Status Register
Description
Figure
14-13, controls the result of detected
Security Engine (SEC) 2.2
(DEUISR)”), if
14-25