MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 752

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.1.8
DMACTRL is writable by the user to configure the DMA block.
the DMACTRL register.
Table 15-14
15-34
Offset eTSEC1:0x2_402C; eTSEC2:0x2_502C
Reset
17–23
0–15
Bits
16
24
25
26
27
W
R
0
TBDSEN TxBD snoop enable.
TDSEN Tx Data snoop enable.
Name
GRS
LE
—
—
—
describes the fields of the DMACTRL register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
DMA Control Register (DMACTRL)
Reserved
Little-endian descriptor mode enable. This bit controls both the reading and writing of descriptors; data
buffers are always transferred in network byte order.
0 RxBDs and TxBDs are interpreted with big-endian byte ordering, as shown in
1 RxBDs and TxBDs are interpreted with little-endian byte ordering. That is, the 16 bits of flags are
Reserved
0 Disables snooping of all transmit frames from memory.
1 Enables snooping of all transmit frames from memory.
0 Disables snooping of all transmit BD memory accesses.
1 Enables snooping of all transmit BD memory accesses.
Reserved
Graceful receive stop. If this bit is set, the Ethernet controller stops receiving frames following completion of
the frame currently being received. (That is, after a valid end of frame was received). The contents of the Rx
FIFO are then written to memory, and the IEVENT[GRSC] is set to indicate that all current receive buffers
have been closed. Because the receive enable bit of the MAC may still be set, the MAC may continue to
receive but the eTSEC ignores the receive data until GRS is cleared. If this bit is cleared, the eTSEC scans
the input data stream for the start of a new frame (preamble sequence and start of frame delimiter) and the
first valid frame received uses the next RxBD.
If GRS is set, the user must monitor the graceful receive stop complete (GRSC) bit in the IEVENT register to
insure that the graceful receive stop was completed. The user can then clear IEVENT[GRSC] and can write
to receive registers that are accessible to both user and the eTSEC hardware without fear of conflict.
0 eTSEC scans input data stream for valid frame.
1 eTSEC stops receiving frames following completion of current frame.
Buffer Descriptors.”
considered a complete half-word unit, the buffer length is considered another complete half-word unit, and
the buffer pointer is considered a complete word unit.
—
Table 15-14. DMACTRL Field Descriptions
Figure 15-9. DMACTRL Register
15 16 17
LE
—
All zeros
Description
23
TDSEN TBDSEN — GRS GTS TOD WWR WOP
24
Figure 15-9
25
26
describes the definition for
27
Section 15.6.7.1, “Data
Freescale Semiconductor
28
Access: Read/Write
29
30
31