MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 937

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

16.3.1.3
HCSPARAMS contains structural parameters such as the number of downstream ports.
the HCSPARAMS register.
Table 16-6
Freescale Semiconductor
31–28
27–24
23–20
19–17
15–12
11–8
Bits
7–5
3–0
16
4
Offset 0x2_3104
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
N_PORTS
R
N_PCC
N_PTT
Name
N_CC
N_TT
31
provides bit descriptions for the HCSPARAMS register.
PPC
—
—
—
PI
Host Controller Structural Parameters (HCSPARAMS)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
28 27
Figure 16-4. Host Controller Structural Parameters (HCSPARAMS)
Reserved, should be cleared.
Number of transaction translators. This is a non-EHCI field. This field indicates the number of embedded
transaction translators associated the module. The reset value of this field is always 1 after the USBDR
controller is configured as a host by writing 0x3 to USBMODE; else, the reset value is always 0. See
Section 16.9.1, “Embedded Transaction Translator Function.”
Ports per transaction translator. This is a non-EHCI field. The number of ports assigned to each
transaction translator. This is equal to N_PORTS.
Reserved, should be cleared.
Port indicators. Indicates whether the ports support port indicator control. The reset value of this field
is always 0 after the USBDR controller is configured as a host by writing 0x3 to USBMODE; else, the
reset value is always 1.
1 The port status and control registers include a R/W field for controlling the state of the port indicator.
Number of companion controllers associated with the DR controller. Always 0.
controller. Always 0.
Reserved, should be cleared.
Power port control. Indicates whether the host controller supports port power control.The reset value of
this field is always 0 after the USBDR controller is configured as a host by writing 0x3 to USBMODE;
else, the reset value is always 1.
1 Ports have power port switches.
Number of ports. Number of physical downstream ports implemented for host applications. The value
of this field determines how many port registers are addressable in the operational register. The reset
value of this field is always 0 after the USBDR controller is configured as a host by writing 0x3 to
USBMODE; else, the reset value is always 1.
Number ports per CC. This field indicates the number of ports supported per internal companion
N_TT
Table 16-6. HCSPARAMS Register Field Descriptions
24 23
N_PTT
20 19
—
17 16 15
PI
1 0 0 0 0 0 0 0 0 0 0 0
Description
N_CC
12 11
N_PCC
8
7
Universal Serial Bus Interface
—
5
Figure 16-4
PPC
Access: Read-only
4
1
0
3
N_PORTS
0
shows
0
16-9
1
0