MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1045

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

The initial SplitXState of the first siTD is Do Start Split. The host controller will visit the first siTD eight
times during frame X. The C-mask bits in micro-frames 0 and 1 are ignored because the state is Do Start
Split. During micro-frame 4, the host controller determines that it can run a start-split (and does) and
changes SplitXState to Do Complete Split. During micro-frames 6 and 7, the host controller executes
complete-splits. Notice the siTD for frame X+1 has it's SplitXState initialized to Do Complete Split. As
the host controller continues to traverse the schedule during H-Frame X+1, it will visit the second siTD
eight times. During micro-frames 0 and 1 it will detect that it must execute complete-splits.
During H-Frame X+1, micro-frame 0, the host controller detects that siTD
zero, saves the state of siTD
transaction state of siTD
results written back to siTD
SplitXState in siTD
start-split for siTD
(transaction-complete is defined in
that is, before all the scheduled complete-splits have been executed, the host controller changes
siTD
transactions. For this example, siTD
micro-frame 1.
During H-Frame X+2, micro-frame 0, the host controller detects that siTD
saves the state of siTD
receives an MDATA response, updates the transfer state, but does not modify the Active bit. The host
controller returns to the context of siTD
to siTD
During H-Frame X+2, micro-frame 1, the host controller detects siTD
the state of siTD
DATA0 response, updates the transfer state and clears the Active bit. It returns to the state of siTD
changes its SplitXState to Do Start Split. At this point, the host controller is prepared to execute start-splits
for siTD
16.6.13 Port Test Modes
EHCI host controllers implement the port test modes Test J_State, Test K_State, Test_Packet, Test
Force_Enable, and Test SE0_NAK as described in the USB Specification Revision 2.0. The required, port
test sequence is (assuming the CF-bit in the CONFIGFLAG register is set):
Freescale Semiconductor
•
•
•
X
[SplitXState] to Do Start Split early and naturally skips the remaining scheduled complete-split
Disable the periodic and asynchronous schedules by clearing the USBCMD[ASE] and
USBCMD[PSE].
Place all enabled root ports into the suspended state by setting the Suspend bit in the PORTSC
register (PORTSC[SUSP]).
Clear USBCMD[RS] (run/stop) and wait for USBSTS[HCH] to transition to a one. Note that an
EHCI host controller implementation may optionally allow port testing with RS set. However, all
host controllers must support port testing with RS cleared and HCH set.
X+2
X+2
.
when it reaches micro-frame 4.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
X+2
X+1
X+1
and fetches siTD
X+2
when it reaches micro-frame 4. If the split-transaction completes early
to Do Start Split. At this point, the host controller is prepared to execute the
X
. If the siTD
and fetches siTD
X
X+1
. The host controller retains the fact that siTD
and fetches siTD
Section 16.6.12.3.5, “Periodic Isochronous—Do Complete
X+1
X+1
X
X+2
split transaction is complete, siTD's Active bit is cleared and
does not receive a DATA0 response until H-Frame X+2,
. It executes another complete-split transaction, receives a
, and traverses it's next pointer without any state change updates
X+1
. As described above, it executes another split transaction,
X
. It executes the complete split transaction using the
X+2
X+2
's S-mask[0] bit is zero, saves
X+1
X
's Back Pointer[T] bit is zero,
is retired and transitions the
's Back Pointer[T] bit is a
Universal Serial Bus Interface
Split”),
X+2
16-117
and