MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 591

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
PCI_REQ[1:2]
PCI_PERR
PCI_REQ0
PCI_PME
Signal
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI parity error
I/O PCI PME signal
I/O PCI bus request
O
O
O
I
I
I
I
Outputs for the bi-directional parity error.
Inputs for the bi-directional parity error.
Outputs for the bi-directional PCI_PME signal. This is an open-drain signal.
Inputs for the bi-directional PCI_PME signal.
the arbiter is disabled. Note that PCI_REQ n is a point-to-point signal. Every master has its own bus
request signal.
Outputs for the bi-directional bus request.
Input for the bi-directional bus request.
PCI bus request
PCI_REQ[n] is a point-to-point signal. Every master has its own bus request signal. Following is the
state meaning for the PCI_REQ[n] input.
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
State
State
State
State
State
State
State
Asserted—The PCI controller, acting as a PCI agent, detected a data parity error. (driven
Negated—No error.
Asserted—Another PCI agent detects a data parity error while this PCI controller is
Negated—No error.
Asserted—Indicates that a power management event has occurred
Negated—Indicates that no power management event has occurred
Asserted—Indicates an agent is requesting a power state change
Negated—Indicates no power state change request
Asserted—The PCI controller is requesting control of the PCI bus to perform a
Negated—The PCI controller does not require use of the PCI bus.
Asserted—Agent 0 is requesting control of the PCI bus to perform a transaction.
Negated—Agent 0 does not require use of the PCI bus.
Asserted—An agent n is requesting control of the PCI bus to perform a transaction.
Negated—An agent n does not require use of the PCI bus.
.
.
by the PCI initiator on reads; driven by the PCI target on writes.)
sourcing data (this PCI controller was acting as the PCI initiator during a write, or is
acting as the PCI target during a read).
transaction.
Input signal on this PCI controller when the arbiter is enabled. Output signal when
Input signals on this PCI controller when the arbiter is enabled. Note that
Description
PCI Bus Interface
13-9