MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1175

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.5.3.5.4, 15-70
15.5.3.5.5, 15-71
15.5.3.5.9, 15-74
15.5.3.6.25, 15-90
15.5.3.6.26, 15-91
15.5.3.3.2, 15-106
15.5.3.3.2, 15-106
15.5.3.9.1, 15-107
15.5.3.10, 15-108
Freescale Semiconductor
0–31
TBYT
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
frames that were involved with collisions. This count does not include preamble/SFD or jam bytes, except for
half-duplex flow control (back-pressure triggered by TCTRL[THDF] = 1). For THDF, the sum total of
‘phantom’ preamble bytes transmitted for flow control purposes is included in the TBYT increment value of
the next frame to be transmitted, up to 65,535 bytes of frame and phantom preamble.
Note that the value of TBYT may be greater than the actual number of bytes transmitted if the frame is
truncated because it exceeds MAXFRM.
Transmit byte counter. Increments by the number of bytes that were put on the wire including fragments of
In Figure 15-39 and Table 15-42, changed the Collision Window to bits 26–31 and
bits 20–25 to Reserved.
In Table 15-43, for bits 16–31, in the Description column, changed the first
paragraph to read:
By default this field is set to 0x0600 (1536 bytes). It sets the maximum Ethernet frame size in both
the transmit and receive directions. (Refer to MACCFG2[Huge Frame].)
In Figure 15-44 corrected the register to reflect that this is a write-only register.
In Table 15-79, for bits 0–31, changed the description to read:
In Table 15-80, changed bits 0–31 to 0–9: Reserved and 10–31: TPKT.
In Figure 14-103, changed the size of ATTRELI[EI] to 18:25
In Table 14-106, in the Bits column, changed the size of ATTRELI[EI] to 18–25
and Reserved to 26–31.
Replaced the first paragraph with the following:
The RQPRMn registers specify the minimum number of BDs required to prevent
flow control being asserted and the total number of Rx BDs in their respective
ring. Whenever the free BD count calculated by the eTSEC for any active ring
drops below the value of RQPRMn[FBTHR] for that ring, link level flow control
will be asserted. Software must not write to RQPRMn while LFC is enabled and
the eTSEC is actively receiving frames. However, software may modify these
registers after disabling LFC by clearing RCTRL[LFC]. Note that packets may be
lost due to lack of RxBDs while RCTRL[LFC] is clear. Software can prevent
packet loss by manually generating pause frames (via TCTRL[TFC_PAUSE]) to
cover the time when RCTRL[LFC] is clear. Figure 15-104 describes the definition
for the RQPRMn register.
Added the following paragraph:
IEEE Standard 1588 compliant timestamping on this device is accomplished using
the per-port transmit timestamping registers within each Ethernet controller
memory space (See Section 15.5.3.2.11, “Transmit Time Stamp Identification
Register (TMR_TXTS1–2_ID),” and Section 15.5.3.2.12, “Transmit Time Stamp
Register (TMR_TXTS1–2_H/L).”) in conjunction with the following common
registers, which are located within the memory space for eTSEC1. Because the
common IEEE Std. 1588 timestamping registers exist within the eTSEC1 memory
space, the eTSEC1 controller must remain enabled in order to use IEEE Std. 1588
timestamping for any Ethernet port.
Revision History
A-17