MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 750

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
The different interface configurations indicated by registers ECNTRL and MACCFG2 are summarized in
Table
15-32
20–24
Bits
19
25
27
28
29
30
31
15-12.
RTBI 1Gbps
RGMII 1Gbps
Interface Mode
SGMIIM
R100M
GMIIM
Name
STEN
RMM
RPM
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
MIB counter statistics enabled.
0 Statistics not enabled
1 Enables internal counters to update
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
Reserved
GMII interface mode. If this bit is set, a PHY with a RGMII interface is expected to be connected. If
cleared, a PHY with an MII or RMII interface is expected. The user should then set MACCFG2[I/F Mode]
accordingly. The state of this status bit is defined during power-on reset.
0 MII or RMII mode interface expected
1 RGMII mode interface expected
Ethernet interfaces. RPM and RMM are never set together. This register can be pin-configured at reset
to 0 or 1.
0 MII in non-reduced-pin mode configuration
1 RGMII or RTBI reduced-pin mode
RGMII/RMII 100 mode. This bit is ignored unless SGMIIM, RPM or RMM are set and MACCFG2[I/F
Mode] is assigned to 10/100 (01).
0 RGMII is in 10 Mbps mode;
1 RGMII is in 100 Mbps mode;
This bit must be cleared for 1-Gbps SGMII operation.
Reduced-pin mode for 10/100 interfaces. If this bit is set, an RMII pin interface is expected. RMM must
be 0 if RPM = 1. This register can be pin-configured at reset to 0 or 1.
0 Non-RMII interface mode
1 RMII interface mode
Serial GMII mode. If this bit is set, a SGMII pin interface is expected to be connected via an on chip
SERDES.
This register can be pin-configured at reset to 0 or 1.
0 SGMII mode disabled. eTSEC connected via a parallel interface.
1 SGMII mode enabled.
Reserved
Reduced-pin mode for Gigabit interfaces. If this bit is set, a reduced-pin interface is expected on
SGMII is in 10 Mbps mode, and every 100th SGMII Reference clock is used to transfer data
SGMII is in 100 Mbps mode, and every 10th SGMII Reference clock is used to transfer data
RMII is in 10 Mbps mode, and every 10th RMII Reference clock is used to transfer data
RMII is in 100 Mbps mode, and data is transferred on every Reference clock
FIFM
Table 15-11. ECNTRL Field Descriptions (continued)
0
0
1
Table 15-12. eTSEC Interface Configurations
GMIIM
0
1
TBIM
1
0
ECNTRL Field
RPM
1
1
Description
R100M
—
—
RMM
—
—
SGMIIM
0
0
Freescale Semiconductor
MACCFG2 Field
I/F Mode
10
10