MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 916

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15-198
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
Set up the MII Mgmt for a write cycle to the external PHY Control register (write the PHY address and Register address),
This enables the external PHY to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),
Set source clock divide by 14, for example, to insure that TSEC_MDC clock speed is not greater than 2.5 MHz.
The AN Advertisement register is at offset address 0x04 from the external PHY address. (in this case 0x11)
The control register (CR) is at offset address 0x00 from the external PHY address. (in this case 0x11)
Write to MII Mgmt Control with 16-bit data intended for the external PHY AN Advertisement register,
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write to MII Mgmt Control with 16-bit data intended for the external PHY Control register,
(Uses the PHY address (0x11) and Register address (6) placed in MIIMADD register)
Set up the MII Mgmt for a write cycle to external the PHY AN Advertisement register
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x2.
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register)
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Table 15-170. RGMII Mode Register Initialization Steps (continued)
Where u must be selected by the user for proper system configuration.
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0110]
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_u0uu_uuuu_uuuu_uuuu]
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0100]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0001]
Perform an MII Mgmt read cycle of AN Expansion Register.
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
read the MIIMSTAT register and check bit 10. (AN Done)
Check to see if PHY has completed Auto-Negotiation.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt write cycle to the external PHY.
This indicates that the eTSEC MII Mgmt bus is idle.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
(write the PHY address and Register address),
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Setup the MII Mgmt clock speed,
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
When MIIMIND[BUSY]=0,
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