MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 251

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

5.5.7
The following initialization sequence for the RTC is recommended:
5.6
The following sections describe theory of operation of the periodic interval timer (PIT) including a
definition of the external signals and the functions it serves. Additionally, the configuration, control, and
status registers are described. Note that individual chapters in this reference manual describe additional
specific initialization aspects for each individual block.
5.6.1
The periodic interval timer (PIT) that generates periodic interrupts for a real-time operating system or an
application software.
Freescale Semiconductor
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1. Write to RTPSR to set the RTC prescaler to the desired value
2. Write to RTLDR to initialize the RTC initial value
3. Write to RTALR to program the RTC alarm value, if needed
4. Write to RTCNR to configure and start the RTC operation: RTC input clock source, second/alarm
RTC every-second interrupt enable/disable mode:
— RTC every-second interrupt enable mode (RTCNR[SIM] = 1)
— RTC every-second interrupt disable mode (RTCNR[SIM] = 0)
RTC alarm interrupt enable/disable mode:
— RTC alarm interrupt enable mode (RTCNR[AIM] = 1)
— RTC alarm interrupt disable mode (RTCNR[AIM] = 0)
RTC internal/external input clock mode:
The input clock to the RTC may be the CSB clock or an external 32.768-kHz crystal.
— RTC uses the internal input clock mode (RTCNR[CLIN] = 0)
— RTC uses the external 32.768-kHz crystal clock (RTCNR[CLIN] = 1)
interrupt mask, RTC clock enable.
Periodic Interval Timer (PIT)
When the counter’s clock is enabled, it continues counting using the previous value.
In this mode the RTC set the RTEVR[SIF] flag and generate an interrupt after the RTC’s 32-bit
counter reaches zero.
In this mode the RTC sets the RTEVR[SIF] flag but does not generate an interrupt after the
RTC’s 32-bit counter reaches zero.
In this mode, the RTC sets the RTEVR[AIF] flag and generates an interrupt each time when the
RTC’s 32-bit counter reaches the RTALR[ALR] value.
In this mode the RTC sets the RTEVR[AIF] flag but does not generate an interrupt when the
RTC’s 32-bit counter reaches the RTALR[ALR] value.
RTC Programming Guidelines
PIT Overview
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
System Configuration
5-43