MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1000

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
after it encounters the end of the periodic schedule. The host controller traverses the periodic schedule by
constructing an array offset reference from the PERIODICLISTBASE and the FRINDEX registers (see
Figure
The end of the periodic schedule is identified by a next link pointer of a schedule data structure having its
T-bit set. When the host controller encounters a T-Bit set during a horizontal traversal of the periodic list,
it interprets this as an End-Of-Periodic-List mark. This causes the host controller to cease working on the
periodic schedule and transitions immediately to traversing the asynchronous schedule. Once this
transition is made, the host controller executes from the asynchronous schedule until the end of the
micro-frame.
When the host controller determines that it is time to execute from the asynchronous list, it uses the
operational register ASYNCLISTADDR to access the asynchronous schedule, as shown in
The ASYNCLISTADDR register contains a physical memory pointer to the next queue head. When the
host controller makes a transition to executing the asynchronous schedule, it begins by reading the queue
head referenced by the ASYNCLISTADDR register. Software must set queue head horizontal pointer
T-bits to a zero for queue heads in the asynchronous schedule.
16.6.6
The USB Specification Revision 2.0 requires that the frame boundaries (SOF frame number changes) of
the high-speed bus and the full- and low-speed bus(es) below USB 2.0 hubs be strictly aligned.
16-72
31
16-43). It fetches the element and begins traversing the graph of linked schedule data structures.
Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
31
Periodic Frame List Base
AsyncListAddr
Operational
USBCMD
Registers
USBSTS
Address
Figure 16-44. General Format of Asynchronous Schedule List
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•
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Figure 16-43. Derivation of Pointer into Frame List Array
Periodic Frame List Element
DWord-Aligned
Address
12
13 12
12 11
H
Frame Index Register
3 2
2 1 0
0
Freescale Semiconductor
Periodic Frame
List
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•
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Figure
16-44.