MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 951

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure
T
during the pre-fill operation the time remaining the [micro]frame is < T
the packet is tried at a later time. Although this is not an error condition and the module eventually
recovers, a mark is made in the scheduler health counter to note the occurrence of a back-off event. When
a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to
make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste
bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated).
Back-offs can be minimized with use of the TSCHHEALTH (T
Freescale Semiconductor
Offset 0x2_3164
Reset 0
31–22
21–16
15–13
p
12–8
Bits
remains before the end of the [micro]frame. If so it proceeds to pre-fill the TX FIFO. If at any time
W
R
31
TXSCHHEALTH Scheduler health counter. Increment when the host controller fails to fill the TX latency FIFO to the
TXFIFOTHRES FIFO burst threshold. Control the number of data bursts that are posted to the TX latency FIFO in
0
Name
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
0
0
—
Figure 16-17. Transmit FIFO Tuning Controls (TXFILLTUNING)
0
Reserved, should be cleared.
host mode before the packet begins on to the bus. The minimum value is 2 and this value should be
a low as possible to maximize USB performance. A higher value can be used in systems with
unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data
transferred from the latency FIFO to USB occurs before it can be replenished from system memory.
This value is ignored if USBMODE[SDIS] (stream disable bit) is set. When USBMODE[SDIS] is set,
the host controller behaves as if TXFIFOTHRES is set to the maximum value.
Reserved, should be cleared.
level programmed by TXFIFOTHRES before running out of time to send the packet before the next
Start-Of-Frame.
This health counter measures the number of times this occurs to provide feedback to selecting a
proper TXSCHOH. Writing to this register clears the counter and this counter stops counting after
reaching the maximum of 31.
Table 16-20. TXFILLTUNING Register Field Descriptions
0
0
0
22 21
0
0
TXFIFOTHRES
0
0
0
0
16 15
0
0
Description
—
0
13 12
0
ff
) parameter described below.
TXSCHHEALTH
0
0
s
then the packet attempt ceases and
0
0
8
0
7
0
Universal Serial Bus Interface
0
0
Access: Read/Write
TXSCHOH
0
0
0
0
16-23
0
0