MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 314

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Arbiter and Bus Monitor
6.3.1.2
When a master owns the address bus and wants to perform another transaction, it can assert bus request
along with REPEAT, to make a repeat request to the arbiter. Consequently, the arbiter asserts bus grant to
the same master if the current address tenure is not being ARTRYed. This happens regardless of the priority
level of bus request from other masters. In another word, “repeat request” overrides the priority scheme.
Even though repeat request can improve the page hit ratio and the overall memory bandwidth efficiency,
it can increase the worst case latency of individual master. Therefore, the arbiter has programmable
counter to limit the maximum number of consecutive transactions that are performed by masters.
Whenever the counter expires, arbiter ignores the REPEAT signal and falls back to the regular arbitration
scheme. PCI master has a dedicated repeat counter as it might need more repeated transactions before
accepting read requests. PCI ordering rules require that the PCI bridge should empty all queued write
operations before any new read operation can begin. See Section 3.2.5, “Transaction Ordering and
Posting,” of the PCI Local Bus Specifications Rev 2.2, for more information.
6-12
•
•
M0 and M3 each gets 1/18 of the bus bandwidth
M1 and M2 each gets 1/36 of the bus bandwidth
Address Bus Arbitration with REPEAT
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
See each bus master’s chapter and
Configuration Register
programming.
Y
X
Z
Figure 6-10. An Example of Priority-Based Arbitration Algorithm
M6
M4
M0
M1
Level 3
Level 2
Level 1
Level 0
(SPCR),” for more details about priority
M5
M3
M2
NOTE
Section 5.3.2.4, “System Priority and
M6 Z M6 Z ...
M6 M4 M6 M5 M6 M0 M6 M4
M6 M5 M6 M3 M6 M4 M6 M5
M6 M1 M6 M4 M6 M5 M6 M0
M6 M4 M6 M5 M6 M3 M6 M4
M6 M5 M6 M2 ...
M4 M5 Y M4 M5 Y ...
M4 M5 M0 M4 M5 M3 M4 M5 M1
M4 M5 M0 M4 M5 M3 M4 M5 M2 ...
M0 M3 X M0 M3 X ...
M0 M3 M1 M0 M3 M2 M0 M3 M1 ...
M1 M2 M1 M2 ...
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