MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 112

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Memory Map
2-8
0x4C–0x4F Reserved
0x68–0xFF Reserved
0x0_0900
0x0_0904
Offset
0x1C
0x2C
0x3C
0x5C
0x0C
0x1C
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x54
0x58
0x60
0x64
0x00
0x04
0x10
0x14
0x18
0x20
System internal interrupt group D priority register
(SIPRR_D)
System internal interrupt mask register (SIMSR_H)
System internal interrupt mask register (SIMSR_L)
System internal interrupt control register (SICNR)
System external interrupt pending register (SEPNR)
System mixed interrupt group A priority register
(SMPRR_A)
System mixed interrupt group B priority register
(SMPRR_B)
System external interrupt mask register (SEMSR)
System external interrupt control register (SECNR)
System error status register (SERSR)
System error mask register (SERMR)
System error control register (SERCR)
System internal interrupt force register (SIFCR_H)
System internal interrupt force register (SIFCR_L)
System external interrupt force register (SEFCR)
System error force register (SERFR)
System critical interrupt vector register (SCVCR)
System management interrupt vector register (SMVCR)
Arbiter configuration register (ACR)
Arbiter timers register (ATR)
Arbiter event register (AER)
Arbiter interrupt definition register (AIDR)
Arbiter mask register (AMR)
Arbiter event attributes register (AEATR)
Arbiter event address register (AEADR)
Arbiter event response register (AERR)
Reset configuration word low register (RCWLR)
Reset configuration word high register (RCWHR)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Register
Table 2-2. Memory Map (continued)
System Arbiter Registers
Reset Module
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
R
R
R
R
R
R
0x0010_0000
0x0000_0000
0x0000_0000
0xFFFF_FFFF
0x0000_0000/
0x0530_9770
0x0000_0000
0x0000_0000
0x0000_0000
0x0530_9770
0x0530_9770
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Special
Reset
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10
11
11
Freescale Semiconductor
Section/Page
4.5.1.1/4-33
4.5.1.2/4-33
8.5.10/8-19
8.5.11/8-20
8.5.12/8-21
8.5.13/8-22
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8.5.17/8-26
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8.5.19/8-27
8.5.20/8-27
8.5.5/8-14
8.5.6/8-15
8.5.6/8-15
8.5.7/8-16
8.5.8/8-18
8.5.9/8-18
6.2.8/6-10
6.2.1/6-2
6.2.2/6-4
6.2.3/6-5
6.2.4/6-6
6.2.5/6-7
6.2.6/6-7
6.2.7/6-9
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