MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 730

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.2
The eTSEC memory mapped registers are accessed by reading and writing to an address comprised of the
base address (specified in IMMRBAR as defined in
address, plus the offset of the specific register to be accessed. Note that all memory-mapped registers must
only be accessed as 32-bit quantities.
Table 15-4
offsets to the memory map table are applicable to each eTSEC. Block base addresses are as follows:
In this table and in the register figures and field descriptions, the following access definitions apply:
15-12
0x2_4008–
0x2_400C
0x2_401C Reserved
0x2_402C DMACTRL—DMA control register
0x2_4000 TSEC_ID*—Controller ID register
0x2_4004 TSEC_ID2*—Controller ID register
0x2_4010 IEVENT—Interrupt event register
0x2_4014 IMASK—Interrupt mask register
0x2_4018 EDIS—Error disabled register
0x2_4020 ECNTRL—Ethernet control register
0x2_4024 Reserved
0x2_4028 PTV—Pause time value register
eTSEC1
Offset
•
•
•
•
•
•
•
eTSEC1 starts at 0x2_4000 address offset
eTSEC2 starts at 0x2_5000 address offset
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Reserved
lists the offset, name, and a cross-reference to the complete description of each register. The
Detailed Memory Map
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 15-3. Module Memory Map Summary (continued)
C00–C3F
C40–DFF
E00–EFF
eTSEC General Control and Status Registers
Name
Table 15-4. Module Memory Map
1
Lossless Flow Control registers
1588 Hardware Assist
Chapter 2, “Memory
—
Access
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
R
R
2
Map.”) plus the block base
0x0030_00F0
0x0124_0106
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
Freescale Semiconductor
15.5.3.1.1/15-22
15.5.3.1.2/15-23
15.5.3.1.3/15-24
15.5.3.1.4/15-27
15.5.3.1.5/15-29
15.5.3.1.6/15-31
15.5.3.1.7/15-33
15.5.3.1.8/15-34
Section/Page
—
—
—