MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 578

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DMA/Messaging Unit
When a DMA channel is halted, its programming model is completely accessible. If the DMA is halted
due to an error condition, the TE (transfer error) bit in the DMA status register (DMASRn) must be cleared
before the transfer can be resumed or a new transfer initiated. Note that the TE bit is not cleared
automatically by hardware.
12.4.4
DMA segment descriptors contain the source and destination addresses of the data segment, the segment
byte count, and a link to the next descriptor. Segment descriptors are built on cache-line (32-byte)
boundaries in either CSB or PCI memory and are linked together into chains using the
next-descriptor-address field.
Application software initializes the current DMA current descriptor address register (DMACDARn) to
point to the first descriptor in the chain. For each descriptor in the chain, the DMA controller starts a new
DMA transfer with the control parameters specified by the descriptor. The DMA controller traverses the
descriptor chain until reaching the last descriptor (with its EOTD bit set).
12-18
Source address
Destination address
Next descriptor address
Byte count
•
Descriptor Field
Leave the channel in the halted state
DMA Segment Descriptors
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Contains the source address of the DMA transfer. After the DMA controller reads the descriptor from
memory, this field will be loaded into the DMA source address register (DMASAR n ).
Contains the destination address of the DMA transfer. After the DMA controller reads the descriptor
from memory, this field will be loaded into the DMA destination address register (DMADAR n ).
Points to the next descriptor in memory. After the DMA controller reads the descriptor from memory,
this field will be loaded into the DMA next descriptor address register (DMANDAR n ).
Contains the number of bytes to transfer. After the DMA controller reads the descriptor from
memory, this field will be loaded into the DMA byte count register (DMABCR n ).
Table 12-17. DMA Segment Descriptor Fields
Description
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