MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 134

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Memory Map
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2-30
0x3_6100–
0x3_6400–
0x3_6800–
0x3_6FFF
0x3_6038
0x3_6040
0x3_6050
0x3_6120
0x3_647F
Depends on reset configuration word high values. See
Depends on reset configuration word high values. See
for details.
Depends on reset configuration word high values. See
details.
Depends on reset configuration word high values. See
details.
Depends on reset configuration word high values. See
Value,”
Depends on reset configuration word high values. See
details.
Depends on reset configuration word high values. See
Value,”
Depends on the reset configuration word high configuration values.
SWCRR[SWEN] reset value directly depends on RCWHR[SWEN] (reset configuration word high).
Reset value is determined from the core PLL configuration of the reset configuration word. See
and Initialization,”
The registers AEATR and AEADR are affected only by the assertion of PORESET
Implementation-dependent reset values are listed in specified section/page.
This register has separate functions for the host and device operation; the host function is listed first in the table.
Cleared on read.
eTSEC2 has the same memory-mapped registers that are described for eTSEC1 from 0x 2_4000 to 0x2_4FFF, except the
offsets are from 0x 2_5000 to 0x2_5FFF.
Offset
for details.
for details.
MDEUICR—MDEU interrupt control register
MDEU ICV size register
MDEUEMR—MDEU end-of-message register
MDEU context memory registers
MDEU key memory
MDEU FIFO
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
for details.
Register
Table 2-2. Memory Map (continued)
Section 5.2.4.4.1, “LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value,”
Section 5.2.4.3.1, “LBLAWBAR0[BASE_ADDR] Reset Value,”
Section 5.2.4.5.1, “PCILAWBAR0[BASE_ADDR] Reset Value,”
Section 5.2.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,”
Section 5.2.4.6.1, “PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset
Section 5.2.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,”
Section 5.2.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset
Access
R/W
R/W
R/W
W
W
W
0x0000_0000_0
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
_0000_1000
_0000_0000
_0000_0000
_0000_0000
_0000_0000
000_0000
Reset
Chapter 4, “Reset, Clocking,
Freescale Semiconductor
14.4.2.10/14-38
14.4.2.11/14-38
14.4.2.12/14-39
14.4.2.13/14-40
14.4.2.8/14-36
14.4.2.9/14-37
Section/Page
for details.
for
for
for