MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 36

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
18.3.1.11
18.3.1.12
18.3.1.13
18.4
18.4.1
18.4.1.1
18.4.1.2
18.4.1.3
18.4.1.4
18.4.2
18.4.3
18.4.4
18.4.4.1
18.4.4.2
18.4.4.3
18.4.5
18.4.5.1
18.4.5.2
18.4.5.3
18.5
19.1
19.2
19.2.1
19.2.2
19.2.3
19.2.3.1
19.2.3.2
19.2.3.3
19.3
19.3.1
19.3.2
19.4
19.4.1
19.4.1.1
19.4.1.2
19.4.1.3
19.4.1.4
xxxvi
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Functional Description................................................................................................. 18-18
DUART Initialization/Application Information .......................................................... 18-22
Overview........................................................................................................................ 19-1
Introduction.................................................................................................................... 19-2
External Signal Descriptions ......................................................................................... 19-6
Memory Map/Register Definition ................................................................................. 19-8
Serial Interface......................................................................................................... 18-19
Baud-Rate Generator Logic ..................................................................................... 18-20
Local Loopback Mode ............................................................................................. 18-20
Errors ....................................................................................................................... 18-21
FIFO Mode .............................................................................................................. 18-21
Features...................................................................................................................... 19-2
SPI Transmission and Reception Process .................................................................. 19-3
Modes of Operation ................................................................................................... 19-3
Overview.................................................................................................................... 19-7
Detailed Signal Descriptions ..................................................................................... 19-7
Register Descriptions................................................................................................. 19-9
Scratch Registers (USCR1 and USCR2) ............................................................. 18-16
Alternate Function Registers (UAFR1 and UAFR2)........................................... 18-16
DMA Status Registers (UDSR1 and UDSR2)..................................................... 18-17
START Bit ........................................................................................................... 18-19
Data Transfer ....................................................................................................... 18-19
Parity Bit .............................................................................................................. 18-19
STOP Bit.............................................................................................................. 18-20
Framing Error ...................................................................................................... 18-21
Parity Error .......................................................................................................... 18-21
Overrun Error....................................................................................................... 18-21
FIFO Interrupts .................................................................................................... 18-21
DMA Mode Select ............................................................................................... 18-22
Interrupt Control Logic........................................................................................ 18-22
SPI as a Master Device .......................................................................................... 19-3
SPI as a Slave Device ............................................................................................ 19-4
SPI Mode Register (SPMODE) ............................................................................. 19-9
SPI Event Register (SPIE) ................................................................................... 19-11
SPI Mask Register (SPIM) .................................................................................. 19-12
SPI Command Register (SPCOM) ...................................................................... 19-14
SPI in Multiple-Master Operation ......................................................................... 19-5
Serial Peripheral Interface
Contents
Chapter 19
Title
Freescale Semiconductor
Number
Page