MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 426

Manufacturer Part Number

MPC8313ZQADDC

Microprocessors - MPU 8313 REV2.2 PB NO ENC

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Manufacturer

BOSTOCK HK LIMITED

Part Number:

MPC8313ZQADDC

Manufacturer:

Freescale Semiconductor

DDR Memory Controller

The DDR memory controller supports many different DDR SDRAM configurations. SDRAMs with

different sizes can be used in the same system. Fifteen multiplexed address signals and three logical bank

select signals support device densities from 64 Mbits to 2 Gbits. Two chip select (CS) signals support one

bank of memory. The DDR SDRAM physical banks can be built from standard memory modules or

directly-attached memory devices. The data path to individual physical banks is bits wide. The DDR

memory controller supports physical bank sizes from 16 Mbytes to 512 Mbytes. The physical banks can

1. All signals are connected in common (in parallel) except for MCS[0:1], MCK, MDM[0:3], and the data bus signals.

2. Each of the MCS[0:1] signals correspond with a separate physical bank of memory.

3. Buffering may be needed if large memory arrays are used.

DDR SDRAM Interface Operation

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Figure 9-22. Example 64-Mbyte DDR SDRAM Configuration

2 Bank’s of 8M ×32 (32 Mbytes each)

To all SDRAM

Memory Data Bus and Strobes

Freescale Semiconductor