MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 723

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
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10- and 100-Mbps MII interface operation
The MAC–PHY interface operates in MII mode by setting MACCFG2[I/F Mode] = 01. The MII
is the media-independent interface defined by the 802.3 standard for 10/100 Mbps operation. The
speed of operation is determined by the TSECn_TX_CLK and TSECn_RX_CLK signals, which
are driven by the transceiver. The transceiver either auto-negotiates the speed, or it may be
controlled by software using the serial management interface (MDC/MDIO signals) to the
transceiver.
Clause 22.2.4 of the IEEE 802.3 specification describes the MII management interface.
10- and 100-Mbps RMII interface operation
The RMII is the reduced media-independent interface defined by the RMII Consortium (March
1998) for 10/100 Mbps operation. The speed of operation is determined by the TSECn_TX_CLK
signal, which is driven by the transceiver.
MAC address recognition options
The options supported are promiscuous, broadcast, exact unicast address match, exact unicast
virtual address match to support router redundancy, and multicast hash match. For detailed
descriptions refer to
eTSEC supports automatic LAN-initiated wake-up during power management through the AMD
Magic Packet™ protocol, as described in
Receive frame parsing options
Frame parsing options are to disable parsing (no TCP/IP off-load), IP header parsing, and TCP or
UDP parsing. Parsing must be enabled to make use of receive queue filing algorithms. The options
are detailed in
Receive queue selection options
Received frames are by default sent to a single buffer descriptor ring. If multiple receive queues
are enabled, a receive queue filer can be programmed with selection criteria to differentiate
received frames and file them to different buffer descriptor rings. See
Service (QoS) Provision,”
TCP/IP transmit options
Frames for transmission may be sent as-is, with IP header processing, or TCP header processing.
The transmit buffer descriptors, described in
(TxBD),”
described in
Transmit queue selection options
The options supported are single transmit queue, priority-based queue selection, and modified
weighted round-robin queueing. These options are described further in
“Transmit Control Register (TCTRL).”
RMON support
Standard Ethernet interface management information base (MIBs) can be generated through the
RMON MIB counters.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
enable these options and operate with parameters prepended to frame buffers, as
Section 15.6.3, “TCP/IP Off-Load.”
Section 15.6.3, “TCP/IP Off-Load.”
Section 15.6.2.7, “Frame Recognition.”
for detailed descriptions.
Section 15.6.2.8, “Magic Packet Mode.”
Section 15.6.7.2, “Transmit Data Buffer Descriptors
Enhanced Three-Speed Ethernet Controllers
Section 15.6.4, “Quality of
Section 15.5.3.2.1,
15-5