MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1202

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

E–E
E
e300 core
e300 core, differences between cores, 7-39
EC_GTX_CLK125 (eTSEC gigabit transmit 125 MHz
EC_MDC (eTSEC management data clock) signal, 15-9
EC_MDIO (eTSEC management data input/output, BIDI)
Error handling
Ethernet controller, see TSEC
eTSEC
Index-4
block diagram, 1-9
overview, 1-7
CSB arbiter and bus monitor, 6-16
DMA/messaging unit, 12-17
DUART, 18-21
eTSEC, 15-158–15-160
I
LBC
block diagram, 15-2
buffer descriptors, 15-185–15-192
clocks
configuration of interfaces, 15-192
error-handling, 15-158–15-160
features, 15-2
functional description, 15-134
gigabit Ethernet channel operation, 15-143
2
C interface
source) signal, 15-9
signal, 15-9
framing error, 18-9, 18-14, 18-19, 18-20, 18-21
overrun error, 18-21
parity error, 18-21
boot sequencer mode, 4-26, 17-16
transfer error registers, 10-25–10-30
receive buffer descriptors (RxBD), 15-190
transmit buffer descriptors (TxBD), 15-186
inputs and outputs, 15-8
management clock out (EC_MDC), 15-9, 15-73
MAC configuration, 15-64
MII interface mode, 15-193
RGMII interface mode, 15-196
RMII interface mode, 15-200
RTBI interface mode, 15-204
flow control, 15-154
frame reception, 15-147
frame recognition, 15-150
frame transmission, 15-145
initialization sequence, 15-143
internal and external loop back, 15-158
inter-packet gap time, 15-158
Magic Packet mode, 15-154
preamble customization, 15-148
RMON support, 15-150
soft reset and reconfiguring procedure, 15-145
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
hash function
initialization/application information, 15-192
interrupts, 15-155–15-158
lossless flow control, 15-175
MAC functionality, 15-64–15-79
memory map/register definition, 15-11
modes of operation, 15-4
overview, 15-1
physical interface connections, 15-134
quality of service (QoS) support, 15-165–15-175
register descriptions, 15-22–15-134
signals
algorithm, 15-152
registers, 15-106–15-108
gigabit Ethernet channel, 15-143
see also eTSEC, configuration
interrupt coalescing, 15-156
interrupt registers, 15-24–15-29
back pressure determination and free buffers, 15-175
software use of hardware-initiated back pressure, 15-177
configuration, 15-64
CSMA/CD control, 15-64
handling packet collisions, 15-65
packet flow control, 15-65
PHY links control, 15-66
registers, 15-67–15-79
detailed memory map, 15-12–15-22
eTSEC2–4 controller offsets, 15-22
top-level module map, 15-11
RMON support, 15-79
media-independent interface (MII), 15-135
reduced gigabit media-independent interface (RGMII),
reduced media-independent interface (RMII), 15-135
reduced ten-bit interface (RTBI), 15-137
receive queue filer, 15-167
transmission scheduling, 15-173
by acronym, see Register Index
DMA attribute registers, 15-108
general control and status registers, 15-22
hash function registers, 15-106–15-108
lossless flow control registers, 15-109–15-110
MAC registers, 15-67–15-79
MIB registers, 15-79–15-106
receive control and status registers, 15-48–15-63
ten-bit interface registers, 15-123–15-134
transmit control and status registers, 15-35–15-46
see also Signals, eTSEC
summary, 15-6
soft reset and reconfiguring procedure, 15-145
by frame count threshold, 15-156
by timer threshold, 15-157
15-136
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Index