MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 1205

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Index
Interrupt
Interrupt handling
Interrupts
IPIC
Freescale Semiconductor
PCI interface
USB, 16-2
clear register, 14-71
mask register, 14-68
status register, 14-70
interrupt types
channel done, 14-64
channel error, 14-64
DUART
eTSEC, 15-155–15-158
general, 14-64
I
LBC interrupt register, 10-28
SEC, 14-75
split transaction, 16-92
block diagram, 8-3
features, 8-4
functional description, 8-28
interrupts
2
C interface
TAP controller, 20-4
bus arbitration unit, 1-13
performance monitor interrupt, 7-12
interrupt control logic, 18-22
interrupt enable and control registers, 18-8–18-10
interrupt registers, 15-24–15-29
calling address match condition, 17-5
flowchart for interrupt service routine, 17-19
interrupt after transfer, 17-21
interrupt enable bit (I2CCR[MIEN]), 17-7
interrupt on START, 17-21
interrupt pending status bit (I2CSR[MIF]), 17-9
interrupt-driven byte-to-byte transfers, 17-2
read of last byte, 17-22
slave mode interrupt service routine guidelines, 17-22
configuration, 8-29
highest priority, 8-31
internal
machine check, 8-35
masking sources, 8-34
mixed
request masking, 8-35
source priorities, 8-31
types, 8-28
for slave transmitter routine, 17-23
loss of arbitration, 17-23
group relative priority, 8-30
group relative priority, 8-30
levels, 8-31
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
ISI (instruction storage interrupt), 7-32
Isochronous transfer descriptor (iTD), see USB interface,
J
Joint test action group, see JTAG interface
JTAG interface
JTAG test and debug interface, 7-12, 7-38
L
LA[27:31] (LBC non-multiplexed address) signals, 10-6
LAD[0:31] (LBC multiplexed address/data) signals, 10-7
LALE (LBC external address latch enable) signal, 10-5,
LBC, see Local bus controller (LBC)
LBCTL (LBC data buffer control) signal, 10-6, 10-44
LBS[0:3] (LBC UPM byte select) signals, 10-5
LCK[0:2] (LBC clock) signals, 10-7
LCS[0:7] (LBC chip select) signals, 10-5
LCS0 (LBC chip select 0) signal, 10-56, 10-69
LGPL0 (LBC GP line 0) signal, 10-6
LGPL1 (LBC GP line 1) signal, 10-6
LGPL2 (LBC GP line 2) signal, 10-6
LGPL3 (LBC GP line 3) signal, 10-6
LGPL4 (LBC GP line 4) signal, 10-6
LGPL5 (LBC GP line 5) signal, 10-6
LGTA (LBC GPCM transfer acknowledge) signal, 10-6,
Little-endian, 16-7
Little-endian mode enable, 7-18
Load/store unit (LSU), 7-1
memory map/register definition, 8-6–8-7
modes of operation, 8-4
overview, 8-1
registers, 8-7–8-28
signals, 8-5–8-6
block diagram, 20-1
registers, 20-3
signals, 20-1–20-3
TAP (test access port) controller, 20-4
TAP controller, 20-4
overview, 7-8
vector generation and calculation, 8-35
core disable mode, 8-5
core enable mode, 8-4
by acronym, see Register Index
cint (critical interrupt), 8-2
int (internal interrupt), 8-2
mcp (machine check processor), 8-2
overview, 8-5
smi (system management interrupt), 8-2
isochronous (high-speed) transfer descriptor (iTD)
10-41
10-55
Index-7
J–L