MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 419

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 9-17
above.
Freescale Semiconductor
10–11 CKE_CNTL Clock enable control. Allows software to globally clear or set all CKE signals issued to DRAM. Once
12–15
16–31 MD_VALUE Mode register value. This field, which specifies the value that is presented on the memory address pins of
Bits
5–7
8
9
SET_REF
SET_PRE
MD_EN
SET_REF Set refresh. Forces an immediate refresh to be issued to the chip select specified by
SET_PRE Set precharge. Forces a precharge or precharge all to be issued to the chip select specified by
Field
MD_SEL
Name
—
shows how DDR_SDRAM_MD_CNTL fields should be set for each of the tasks described
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Mode register select. MD_SEL specifies one of the following:
Note that MD_SEL contains the value that is presented onto the memory bank address pins (MBA n ) of the
DDR controller.
000 MR
001 EMR
010 EMR2
011 EMR3
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit is set by software and cleared by hardware once the
command has been issued.
0 Indicates that no refresh command needs to be issued.
1 Indicates that a refresh command is ready to be issued.
DDR_SDRAM_MD_CNTL[CS_SEL]. This bit is set by software and cleared by hardware once the
command has been issued.
0 Indicates that no precharge all command needs to be issued.
1 Indicates that a precharge all command is ready to be issued.
software has forced the value driven on CKE, that value continues to be forced until software clears the
CKE_CNTL bits. At that time, the DDR controller continues to drive the CKE signals to the same value
forced by software until another event causes the CKE signals to change (such as, self refresh entry/exit,
power down entry/exit).
00 CKE signals are not forced by software.
01 CKE signals are forced to a low value by software.
10 CKE signals are forced to a high value by software.
11 Reserved
Reserved
the DDR controller during a mode register set command, is significant only when this register is used to
issue a mode register set command or a precharge or precharge all command.
For a mode register set command, this field contains the data to be written to the selected mode register.
For a precharge command, only bit five is significant:
0 Issue a precharge command; MD_SEL selects the logical bank to be precharged
1 Issue a precharge all command; all logical banks are precharged
• During a mode select command, selects the SDRAM mode register to be changed
• During a precharge command, selects the SDRAM logical bank to be precharged. A precharge all
• During a refresh command, this field is ignored.
Mode Register Set
Table 9-16. DDR_SDRAM_MD_CNTL Field Descriptions (continued)
command ignores this field.
Table 9-17. Settings of DDR_SDRAM_MD_CNTL Fields
1
0
0
Refresh
0
1
0
Description
Precharge
0
0
1
Clock Enable Signals
DDR Memory Controller
Control
—
—
—
9-25