MPC8313ZQADDC Freescale Semiconductor, MPC8313ZQADDC Datasheet - Page 178

• Manufacturer Part Number: MPC8313ZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Reset, Clocking, and Initialization
4.3.2
The reset configuration words control the clock ratios and other basic device functions such as PCI host
or agent mode, boot location, and endian mode. The reset configuration words are loaded from NOR Flash,
NAND Flash, or the I
Section 4.3.1, “Reset Configuration Signals,”
Although the configuration reset words are loaded during hard reset flows, the clocks and PLL modes are
reset only when PORESET is asserted during a power-on reset flow. See
The values of fields in the reset configuration words registers (RCWLR and RCWHR) reflect only their
state during the reset flow. Some of these parameters and modes can be modified by changing their values
in the memory-mapped registers of other units, which does not affect RCWLR and RCWHR.
The reset configuration settings are accessible to software through the following read-only
memory-mapped registers:
See
4-12
Configuration
I
2
C EEPROM
•
•
•
•
Words
Section 4.5, “Memory Map/Register Definitions.”
Yes
Yes
Yes
No
No
No
Reset configuration word low register (RCWLR)
Reset configuration word high register (RCWHR)
Reset status register (RSR)
System PLL mode register (SPMR)
Reset Configuration Words
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
SYS_CLK_IN
(Host Mode)
Frequency
66 MHz
33 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Table 4-7. Selecting Reset Configuration Input Signals (continued)
2
C interfaces or from hard-coded values during the power-on or hard reset flows. See
CFG_CLKIN_DIV
(Host Mode)
0
1
1
0
1
1
(Agent Mode)
Frequency
PCI_CLK
for information on the reset configuration word source.
33 MHz
33 MHz
66 MHz
33 MHz
66 MHz
66 MHz
0000
(RCW loaded from NOR
Flash)
0100 (I
0100 (I
0100 (I
0001 (RCW loaded from
8-bit small page NAND
Flash)
0101 (RCW loaded from
8-bit large page NAND
Flash)
CFG_RESET_
SOURCE[0:3]
2
2
2
C EEPROM)
C EEPROM)
C EEPROM)
Section 4.2.1.2, “Reset Actions.”
Reset Sequence
213068/106534
SYS_CLK_IN/
30420/15210
Duration in
PCI_CLK
106534
106534
Cycles
Freescale Semiconductor
23024
45284
Duration
3196
1598
3196
456
345
679
μ
μ
μ
μ
μ
μ
s
s
s
s
s
s